Modifying work function in PMOS devices by counter-doping

Patent metadata

Field	Value
Publication number	US-8969972-B2
Application number	US-201313750186-A
Country	US
Kind code	B2
Filing date	Jan 25, 2013
Priority date	May 3, 2006
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

First claim

What is claimed is:

1. A structure comprising:
a semiconductor substrate;
a first p-type transistor device in a memory region in the semiconductor substrate, the first p-type transistor device comprising a first gate electrode; and
a second p-type transistor device in a peripheral circuit, the second p-type transistor device comprising a second gate electrode,
wherein a work function of the first gate electrode is different from a work function of the second gate electrode,…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Lee Chun-Yi
• Chuang Harry-Hak-Lay
• Wang Ping-Wei
• Thei Kong-Beng

Classifications

• G11C11/412 Primary

  Physics · mapped topic

• Y10S438/919

  Cross-Sectional Technologies · mapped topic

• H10D64/021

  Electricity · mapped topic

• H10D62/822

  Electricity · mapped topic

• H10D30/601

  Electricity · mapped topic