Hot-carrier injection programmable memory and method of programming such a memory
US-9224482-B2 · Dec 29, 2015 · US
Semiconductor integrated circuit and method of producing the same
US8969944B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8969944-B2 |
| Application number | US-201113697905-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 13, 2011 |
| Priority date | May 14, 2010 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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Abstract
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Provided is a semiconductor integrated circuit that uses a novel vertical MOS transistor that is free of interference between cells, that enables the short-channel effect to be minimized, that does not have hot electron injection, and that does not require the formation of shallow junction. Also provided is a method of producing the semiconductor integrated circuit. A memory cell 1 in the semiconductor integrated circuit is provided with: a semiconductor pillar 2 that serves as a channel; a floating gate 5 that circumferentially covers the semiconductor pillar 2 via a tunnel insulation layer 6 on the outer circumference of the semiconductor pillar 2 ; and a control gate 4 that circumferentially covers the semiconductor pillar via an insulating layer 8 on the outer circumference of the semiconductor pillar 2 , and that circumferentially covers the floating gate 5 via an insulating layer 7 on the outer circumference of the floating gate.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor integrated circuit in which a plurality of memory cells are serially-connected in an axial direction, comprising: a semiconductor pillar provided in the axial direction that serves as a channel; a floating gate that circumferentially covers the side face of the semiconductor pillar or covers a part of the semiconductor pillar to have an interval from the outer circumference of the semiconductor pillar; a control gate that circumferentiall…
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Electricity · mapped topic
Physics · mapped topic
- G11C16/0425Primary
Physics · mapped topic
Physics · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8969944B2 cover?
- Provided is a semiconductor integrated circuit that uses a novel vertical MOS transistor that is free of interference between cells, that enables the short-channel effect to be minimized, that does not have hot electron injection, and that does not require the formation of shallow junction. Also provided is a method of producing the semiconductor integrated circuit. A memory cell 1 in the sem…
- Who is the assignee on this patent?
- Endoh Tetsuo, Moon-Sik Seo, Univ Tohoku
- What technology area does this patent fall under?
- Primary CPC classification G11C16/0425. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).