Electronic device based on multilayer thin film and method for manufacturing the same using a three-dimensional structure
US-2024309503-A1 · Sep 19, 2024 · US
Semiconductor device
US8969937B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8969937-B2 |
| Application number | US-201414291069-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 30, 2014 |
| Priority date | May 2, 2012 |
| Publication date | Mar 3, 2015 |
| Grant date | Mar 3, 2015 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A semiconductor device includes a first insulating layer, a contact plug formed in the first insulating layer, a first etch stop layer over the first insulating layer, a second etch stop layer over the first etch stop layer, a second insulating layer over the second etch stop layer and having a contact opening over the contact plug, and a conductive layer disposed in the contact opening and over the contact plug. The contact opening is substantially free of the second etch stop layer, and the first etch stop layer is present in the contact opening.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device, comprising: a first insulating layer; a contact plug formed in the first insulating layer; a first etch stop layer over the first insulating layer; a second etch stop layer over the first etch stop layer; a second insulating layer over the second etch stop layer and having a contact opening over the contact plug; and a conductive layer disposed in the contact opening and over the contact plug; wherein the contact opening i…
Assignees
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8969937B2 cover?
- A semiconductor device includes a first insulating layer, a contact plug formed in the first insulating layer, a first etch stop layer over the first insulating layer, a second etch stop layer over the first etch stop layer, a second insulating layer over the second etch stop layer and having a contact opening over the contact plug, and a conductive layer disposed in the contact opening and ove…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification H10D1/042. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).