N-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD)

Patent metadata

Field	Value
Publication number	US-9214540-B2
Application number	US-201213731181-A
Country	US
Kind code	B2
Filing date	Dec 31, 2012
Priority date	Dec 31, 2012
Publication date	Dec 15, 2015
Grant date	Dec 15, 2015

Abstract

One or more techniques or systems for forming an n-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD) are provided herein. In some embodiments, the NMOS transistor includes a first region, a first n-type plus (NP) region, a first p-type plus (PP) region, a second NP region, a second PP region, a shallow trench isolation (STI) region, and a gate stack. In some embodiments, the first PP region is between the first NP region and the second NP region. In some embodiments, the second NP region is between the first PP region and the second PP region, the gate stack is between the first PP region and the second NP region, the STI region is between the second NP region and the second PP region. Accordingly, the first PP region enables ESD current to discharge based on a low trigger voltage for the NMOS transistor.

First claim

What is claimed is:

1. An n-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD), comprising:
a first region comprising a p-type well (PW) region, a first native NMOS blocked implant (NTN) region, and a second NTN region;
a first n-type plus (NP) region above at least some of the first NTN region;
a first p-type plus (PP) region above at least some of at least one of the first NTN region or the PW region;
a dummy gate stack between the first NP…

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Tsai Tsung-Che
• Lee Jam-Wem

Classifications

• H10D89/813

  Electricity · mapped topic

• H10D64/115

  Electricity · mapped topic

• H10D62/393

  Electricity · mapped topic

• H10D62/177

  Electricity · mapped topic

• H10D62/137

  Electricity · mapped topic