Pattern for ultra-high voltage semiconductor device manufacturing and process monitoring

Patent metadata

Field	Value
Publication number	US-8969870-B2
Application number	US-201313886656-A
Country	US
Kind code	B2
Filing date	May 3, 2013
Priority date	Mar 12, 2013
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

A pattern for use in the manufacture of semiconductor devices is provided which, according to an example embodiment, may comprise at least one second field region comprising a main array of dies, each having a height of Y 1 and a width of X 1 , and the main array having a height of Y 3 . The pattern according to the example embodiment may further include at least one first field region comprising a monitoring region having a height of Y 2 and a width of X 2 and an auxiliary die region having a height of Y 2 and comprising an auxiliary array of dies. The dimensions of the various regions may be proportional to one another, such that X 2 =n 1 ×X 1 +adjustment 1 , Y 2 =n 3 ×Y 1 +adjustment 3 , and Y 3 =n 4 ×Y 2 +adjustment 4 , n 1 , n 3 , and n 4 being integers.

First claim

What is claimed:

1. A semiconductor device comprising:
at least one second field region comprising a main array of dies, each of the dies having a height of Y 1 and a width of X 1 , and the main array having a height of Y 3 ; and
at least one first field region comprising:
a monitoring region having a height of Y 2 and a width of X 2 , and
an auxiliary die region comprising an auxiliary array of dies;

wherein:
X 2 =n 1 ×X 1 +adjustment 1 ;
Y 2 =…

Assignees

• Macronix Int Co Ltd

Inventors

• Lin Chen-Yuan
• Chan Ching-Lin
• Lin Cheng-Chi
• Lien Shih-Chin

Classifications

• H10P74/203

  Electricity · mapped topic

• H10P74/277 Primary

  Electricity · mapped topic

• H10D89/00

  Electricity · mapped topic

• H01L22/34 Primary

  Electricity · mapped topic

• H01L22/12

  Electricity · mapped topic