Memory device having trapezoidal bitlines and method of fabricating same

Patent metadata

Field	Value
Publication number	US-8957472-B2
Application number	US-201213357252-A
Country	US
Kind code	B2
Filing date	Jan 24, 2012
Priority date	Jan 12, 2005
Publication date	Feb 17, 2015
Grant date	Feb 17, 2015

Abstract

A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.

First claim

What is claimed is:

1. A method of fabricating a memory device onto a semiconductor substrate, the method comprising:
forming a charge trapping dielectric stack over the semiconductor substrate;
forming a gate electrode over the charge trapping dielectric stack;
forming a pair of liners adjacent to and in physical contact with lateral sidewalls of the charge trapping dielectric stack and the gate electrode, the pair of liners defining a pair of bitline openings; and
forming…

Assignees

• Melik-Martirosian Ashot
• Ramsbey Mark T
• Randolph Mark W
• Spansion Llc

Inventors

• Melik-Martirosian Ashot
• Ramsbey Mark T
• Randolph Mark W

Classifications

• H10D30/691 Primary

  Electricity · mapped topic

• H10D30/0413

  Electricity · mapped topic

• H01L27/11568

  Electricity · mapped topic

• H01L29/66833

  Electricity · mapped topic

• H01L29/7923 Primary

  Electricity · mapped topic