Antipodal-mapping-based encoders and decoders

US8949693B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8949693-B2
Application numberUS-201114002790-A
CountryUS
Kind codeB2
Filing dateMar 4, 2011
Priority dateMar 4, 2011
Publication dateFeb 3, 2015
Grant dateFeb 3, 2015

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Abstract

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Examples of the present invention include an electronic-memory-system component. The electronic-memory-system component includes an array of data-storage elements and an encoder that receives input data, processes the input data as a two-dimensional array of bits by carrying out two passes, in one pass subjecting a portion of each row of the two-dimensional array of bits having more than a threshold weight to a first weight-reduction operation, and, in another pass, subjecting a portion of each considered column of the two-dimensional array of bits having more than a threshold weight to a second weight-reduction operation, one of the first and second weight-reduction operations employing an antipodal mapping and the other of the first and second weight-reduction operations employing bit inversion, generates a codeword corresponding to the input data, and stores the codeword in the array of data-storage elements.

First claim

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The invention claimed is: 1. An electronic-memory-system component comprising: an array of data-storage elements; and an encoder that receives input data, processes the input data as a two-dimensional array of bits by carrying out two passes, in one pass subjecting a portion of each row of the two-dimensional array of bits having more than a threshold weight to a first weight-reduction operation, and, in another pass, subjecting a portion of each considered column of the two-…

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What does patent US8949693B2 cover?
Examples of the present invention include an electronic-memory-system component. The electronic-memory-system component includes an array of data-storage elements and an encoder that receives input data, processes the input data as a two-dimensional array of bits by carrying out two passes, in one pass subjecting a portion of each row of the two-dimensional array of bits having more than a thre…
Who is the assignee on this patent?
Ordentlich Erik, Roth Ron M, Hewlett Packard Development Co
What technology area does this patent fall under?
Primary CPC classification G11C13/0002. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).