Methods for shallow trench isolation formation in a silicon germanium layer
US-2015371889-A1 · Dec 24, 2015 · US
Method for forming dummy gate
US8946030B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8946030-B2 |
| Application number | US-201314109231-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 17, 2013 |
| Priority date | Dec 18, 2012 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
Disclosed is a method of forming a dummy gate in manufacturing a field effect transistor. The method includes a first process of exposing a workpiece having a polycrystalline silicon layer to plasma of HBr gas, and a second process of further exposing the workpiece to the plasma of HBr gas after the first process. The first process includes etching the polycrystalline silicon layer to form a dummy semiconductor part having a pair of side surfaces from the polycrystalline silicon layer, and forming a protection film based on a by-product of etching on the pair of side surfaces in such a manner that the thickness of the protection film becomes smaller toward a lower end of the dummy semiconductor part.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of forming a dummy gate in manufacturing a field effect transistor, the method comprising: a first process of exposing a workpiece having a polycrystalline silicon layer formed on an insulating layer and a semiconductor part to microwave-generated plasma of HBr gas and O 2 gas, the first process including etching the polycrystalline silicon layer until the insulating layer and the semiconductor part are exposed to form a dummy semiconductor part ha…
Assignees
Inventors
Classifications
- H10P50/268Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10P10/00Primary
Electricity · mapped topic
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US8946030B2 cover?
- Disclosed is a method of forming a dummy gate in manufacturing a field effect transistor. The method includes a first process of exposing a workpiece having a polycrystalline silicon layer to plasma of HBr gas, and a second process of further exposing the workpiece to the plasma of HBr gas after the first process. The first process includes etching the polycrystalline silicon layer to form a du…
- Who is the assignee on this patent?
- Tokyo Electron Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10P50/268. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).