Hierarchical global clock tree

Patent metadata

Field	Value
Publication number	US-8933734-B2
Application number	US-201414159869-A
Country	US
Kind code	B2
Filing date	Jan 21, 2014
Priority date	Sep 14, 2009
Publication date	Jan 13, 2015
Grant date	Jan 13, 2015

Abstract

Methods, systems, and circuits for forming and operating a global hierarchical clock tree are described. The global hierarchical clock tree may comprise a clock circuit that operates to provide clock signals to a core circuit surrounded by the clock circuit. The clock circuit may include two or more first and second clock generator modules to generate a first and a second set of clock signals, respectively. The first and second clock modules may be located so that the first set of clock signals experience approximately equal first latencies and the second set of clock signals experience approximately equal second latencies. Additional methods, systems, and circuits are disclosed.

First claim

What is claimed is:

1. An integrated circuit comprising:
a clock circuit configured to provide clock signals to a core circuit, the clock circuit comprising:
a plurality of clock-generator modules configured to generate a plurality of first-level clock signals; and
a hierarchy of clock modules arranged in one or more levels including a first level, each level including a plurality of clock modules that are each configured to receive at least one clock signal corresponding to th…

Assignees

• Achronix Semiconductor Corp

Inventors

• Sunkavalli Ravi
• Nimaiyar Rahul
• Kurlagunda Ravi
• Bantval Vijay

Classifications

• G06F1/10 Primary

  Physics · mapped topic

• G06F1/06 Primary

  Physics · mapped topic