Interposer devices having multiple sets of components formed thereon

Patent metadata

Field	Value
Publication number	US-2026068701-A1
Application number	US-202519302298-A
Country	US
Kind code	A1
Filing date	Aug 18, 2025
Priority date	Aug 27, 2024
Publication date	Mar 5, 2026
Grant date	—

Abstract

An interposer device includes a first core, a second core hybrid bonded to the first core, a first redistribution layer (RDL), and a second RDL. The first core and the second core are located between the first RDL and the second RDL.

First claim

What is claimed is:

1 . An interposer device comprising:
a first core; a second core hybrid bonded to the first core; a first redistribution layer (RDL) layer; and a second RDL; wherein the first core and the second core are located between the first RDL and the second RDL.

2 . The interposer device of claim 1 , further comprising a first through-substrate via (TSV) connected to the first RDL and a second TSV connected to the second RDL, wherein, to hybrid bond the first core to the second core, the first TSV is bonded to the second TSV.

3 . The interposer device of claim 1 , wherein the first core comprises a first core substrate embedded within the first dielectric layer, wherein the second core comprise a second core substrate embedded within a second dielectric layer, and wherein, to hybrid bond the first core to the second core, the first dielectric layer is bonded to the second dielectric layer.

4 . The interposer device of claim 3 , wherein the first dielectric layer and the second dielectric layer each comprise an inorganic dielectric material.

5 . The interposer device of claim 3 , wherein the first core substrate and the second core substrate are each a silicon core substrate.

6 . A system comprising:
an interposer device; a first set of components formed on a first side of the interposer device; and a second set of components formed on second side of the interposer device opposite the first side; wherein the interposer device comprises:
a first core;
a second core hybrid bonded to the first core;
a first redistribution layer (RDL) layer; and
a second RDL;
wherein the first core and the second core are located between the first RDL and the second RDL.

7 . The system of claim 6 , further comprising a first through-substrate via (TSV) connected to the first RDL and a second TSV connected to the second RDL, wherein, to hybrid bond the first core to the second core, the first TSV is bonded to the second TSV.

8 . The system of claim 6 , wherein the first core comprises a first core substrate embedded within the first dielectric layer, wherein the second core comprise a second core substrate embedded within a second dielectric layer, and wherein, to hybrid bond the first core to the second core, the first dielectric layer is bonded to the second dielectric layer.

9 . The system of claim 8 , wherein the first dielectric layer and the second dielectric layer each comprise an inorganic dielectric material.

10 . The system of claim 8 , wherein the first core substrate and the second core substrate are each a silicon core substrate.

11 . The system of claim 6 , wherein the first set of components comprises a first memory component, and wherein the second set of components comprises a second memory component.

12 . The system of claim 11 , wherein the first memory component and the second memory component are each a high-bandwidth memory (HBM) component.

13 . The system of claim 6 , wherein the first set of components comprises a first processor component comprising one or more first processing units, and wherein the second set of components comprises a second processor component comprising one or more second processing units.

14 . The system of claim 13 , wherein the one or more first processing units comprise at least one of: one or more central processing units (CPUs), one or more graphics processing units (GPUs), one or more data processing units (DPUs), one or more neural processing units (NPUs), one or more extensible processing units (XPUs), or one or more application-specific integrated circuits (ASICs).

15 . A system comprising:
an interposer device; a first high-bandwidth memory (HBM) component formed on a first side of the interposer device; and a second HBM component formed on second side of the interposer device opposite the first side; wherein the interposer device comprises:
a first core comprising:
a first redistribution layer comprising a first dielectric layer;
a first through-substrate via (TSV) connected to the first redistribution layer; and
a first core substrate embedded within the first dielectric layer, wherein the first TSV extends through the first core substrate; and

a second core hybrid bonded to the first core, the second core comprising;
a second redistribution layer comprising a second dielectric layer;
a second TSV connected to the first redistribution layer; and
a second core substrate embedded within the second dielectric layer,

wherein the second TSV extends through the second core substrate.

16 . The system of claim 15 , further comprising a first processor component formed on the first side and a second processor component formed on the second side.

17 . The system of claim 16 , wherein the first process component comprises at least one of: one or more central processing units (CPUs), one or more graphics processing units (GPUs), one or more data processing units (DPUs), one or more neural processing units (NPUs), one or more extensible processing units (XPUs), or one or more application-specific integrated circuits (ASICs).

18 . The system of claim 15 , wherein the first dielectric layer and the second dielectric layer each comprise an inorganic dielectric material.

19 . The system of claim 15 , wherein the first core substrate and the second core substrate are each a silicon core substrate.

Assignees

• Applied Materials Inc

Inventors

• Chiruvolu Shivkumar
• Bhansali Ameet S
• Verhaverbeke Steven

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/698

  Semiconductor materials that are electrically insulating, e.g. undoped silicon · CPC title

• H10W70/611 Primary

  for connecting multiple chips together · CPC title

• H10B80/00

  Assemblies of multiple devices comprising at least one memory device covered by this subclass · CPC title