Semiconductor device and method of manufacturing the semiconductor device

Patent metadata

Field	Value
Publication number	US-2026052688-A1
Application number	US-202418962090-A
Country	US
Kind code	A1
Filing date	Nov 27, 2024
Priority date	Aug 14, 2024
Publication date	Feb 19, 2026
Grant date	—

Abstract

A semiconductor device includes a first gate structure including alternately stacked first conductive layers and first insulating layers, a second gate structure positioned on the first gate structure and including alternately stacked second conductive layers and second insulating layers, and channel structures extending through the first gate structure and the second gate structure and having a first width. The semiconductor device also includes first contact vias extending through the second gate structure and into the first gate structure, being respectively connected to the first conductive layers, respectively including first sub-vias merged in a horizontal direction, and having a second width greater than the first width. The semiconductor device further includes second contact vias extending into the second gate structure, being respectively connected to the second conductive layers, respectively including second sub-vias merged in the horizontal direction, and having a third width greater than the first width.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first gate structure including first conductive layers and first insulating layers alternately stacked with each other; a second gate structure positioned on the first gate structure, the second gate structure including second conductive layers and second insulating layers alternately stacked with each other; channel structures extending through the first gate structure and the second gate structure, the channel structures having a first width; first contact vias extending through the second gate structure and into the first gate structure, the first contact vias respectively connected to the first conductive layers, the first contact vias respectively including first sub-vias merged in a horizontal direction, and the first contact vias having a second width greater than the first width; and second contact vias extending into the second gate structure, the second contact vias respectively connected to the second conductive layers, the second contact vias respectively including second sub-vias merged in the horizontal direction, and the second contact vias having a third width greater than the first width.

2 . The semiconductor device of claim 1 , wherein at least one of the first contact vias and the second contact vias has a dumbbell shape or a clover shape in a plane.

3 . The semiconductor device of claim 1 , wherein the first contact vias include a first uneven portion on a sidewall in a plane.

4 . The semiconductor device of claim 3 , wherein a portion where the first sub-vias are in contact with each other forms a concave portion of the first uneven portion, and
each of the first sub-vias forms a convex portion of the first uneven portion.

5 . The semiconductor device of claim 1 , wherein the first contact vias include a second uneven portion on a sidewall in a cross-section.

6 . The semiconductor device of claim 5 , wherein the second uneven portion includes protrusions in which the first contact vias protrude toward the first conductive layers or the second conductive layers.

7 . The semiconductor device of claim 1 , wherein each of the first contact vias includes at least two of the first sub-vias.

8 . The semiconductor device of claim 1 , further comprising:
a third gate structure positioned on the second gate structure, the third gate structure including third conductive layers and third insulating layers alternately stacked with each other; and third contact vias extending into the third gate structure, the third contact vias respectively connected to the third conductive layers, the third contact vias respectively including third sub-vias merged in the horizontal direction, and the third contact vias having a fourth width greater than the first width.

9 . The semiconductor device of claim 8 , wherein the fourth width is less than at least one of the second width and the third width.

10 . The semiconductor device of claim 8 , further comprising:
supports extending through the first gate structure, the second gate structure, and the third gate structure; and an interlayer insulating layer positioned on the third gate structure.

11 . The semiconductor device of claim 10 , wherein the first contact vias and the second contact vias extend through the third gate structure and the interlayer insulating layer.

12 . The semiconductor device of claim 10 , wherein the interlayer insulating layer covers the channel structures and the supports.

13 . The semiconductor device of claim 1 , wherein the third width is substantially the same as the second width.

14 . The semiconductor device of claim 1 , wherein the first contact vias have a fifth width greater than the second width in the first gate structure.

15 . A method of manufacturing a semiconductor device, the method comprising:
forming a first stack by alternately stacking first material layers and second material layers; forming a second stack by alternately stacking third material layers and fourth material layers on the first stack; forming first sub-via holes extending through the second stack; forming preliminary first via holes by expanding the first sub-via holes so that at least two of the first sub-via holes are interconnected; forming first via holes of different depths by extending the preliminary first via holes into the first stack; and forming first contact vias in the first via holes.

16 . The method of claim 15 , wherein forming the preliminary first via holes comprises:
selectively removing the third material layers; and selectively removing the fourth material layers.

17 . The method of claim 15 , wherein forming the first via holes comprises:
removing a first material layer of the first material layers; removing a second material layer of the second material layers; and forming the first via holes of different depths by removing additional first and second material layers to achieve the different depths.

18 . The method of claim 15 , wherein the preliminary first via holes are extended so that the first via holes expose the respective second material layers.

19 . The method of claim 15 , further comprising:
forming a third stack by alternately stacking fifth material layers and sixth material layers on the second stack; forming second sub-via holes connected to the first sub-via holes through the third stack; forming a protective layer on the third stack; forming fourth sub-via holes connected to the second sub-via holes through the protective layer; and forming first openings by removing a portion of the protective layer so that at least two of the fourth sub-via holes are interconnected.

20 . The method of claim 19 , wherein the preliminary first via holes are formed through the first openings.

21 . The method of claim 19 , further comprising:
forming third sub-via holes extending through the third stack; forming fifth sub-via holes connected to the third sub-via holes through the protective layer; forming second openings by removing a portion of the protective layer so that at least two of the fifth sub-via holes are interconnected; forming preliminary second via holes by expanding the third sub-via holes so that at least two of the third sub-via holes are interconnected through the second openings; forming second via holes of different depths by extending the preliminary second via holes into the second stack; and forming second contact vias in the second via holes.

22 . The method of claim 19 , further comprising:
forming sixth sub-via holes extending through the protective layer and the third stack; forming third openings by removing a portion of the protective layer to so that at least two of the sixth sub-via holes are interconnected; forming preliminary third via holes by expanding the sixth sub-via holes so that at least two of the sixth sub-via holes are interconnected through the third openings; forming third via holes of different depths by extending the preliminary third via holes into the third stack; and forming third contact vias in the third via holes.

23 . The method of claim 15 , further comprising:
forming first channel holes extending through the first stack; forming trenches positioned to correspond to the first sub-via holes, respectively, in the first stack; and forming buffer layers in the trenches.

24 . The method of claim 23 , wherein the first sub-via holes expose t

Assignees

• Sk Hynix Inc

Inventors

• Kwak Rho Gyu
• Jang Jung Shik
• Choi Won Geun
• Park Mi Seong
• Park In Su
• Yang Na Yeong
• Choi Seok Min

Classifications

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B41/10

  characterised by the top-view layout · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B41/50

  characterised by the boundary region between the core region and the peripheral circuit region · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title