Three-dimensional memory devices and methods for forming the same

Patent metadata

Field	Value
Publication number	US-2026047095-A1
Application number	US-202519362866-A
Country	US
Kind code	A1
Filing date	Oct 20, 2025
Priority date	Aug 23, 2021
Publication date	Feb 12, 2026
Grant date	—

Abstract

A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a first angled structure, and a first diameter of the memory film at the bottom portion below the first angled structure is smaller than a second diameter of the memory film at an upper portion above the first angled structure.

First claim

What is claimed is:

1 . A memory device, comprising:
a stack structure comprising interleaved first conductive layers and first dielectric layers; and a channel structure extending through the stack structure along a first direction, the channel structure comprising a semiconductor channel, a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer; and a polysilicon layer under the stack structure and in contact with the semiconductor channel, wherein the tunneling layer, the storage layer, and the blocking layer are in direct contact with the polysilicon layer.

2 . The memory device of claim 1 , further comprising a gate line slit extending through the stack structure along the first direction and in contact with the polysilicon layer.

3 . The memory device of claim 2 , wherein
the gate line slit comprises a second conductive layer and a second dielectric layer between the second conductive layer and the stack structure; and the second conductive layer is in contact with the polysilicon layer.

4 . The memory device of claim 1 , further comprising a first contact pad in contact with the polysilicon layer, wherein the polysilicon layer is between the stack structure and the first contact pad in the first direction.

5 . The memory device of claim 1 , further comprising:
a contact structure over the polysilicon layer and extending along the first direction in or out of the stack structure; and a second contact pad extending through the polysilicon layer along the first direction and in contact with the contact structure.

6 . The memory device of claim 1 , wherein a first thickness of the blocking layer at a bottom portion of the channel structure is larger than a second thickness of the blocking layer at an upper portion of the channel structure.

7 . The memory device of claim 6 , further comprising a dielectric core in the semiconductor channel,
wherein the dielectric core is surrounded by the semiconductor channel at the bottom portion of the channel structure, and a first diameter of the dielectric core at the bottom portion of the channel structure is smaller than a second diameter of the dielectric core at the upper portion of the channel structure.

8 . The memory device of claim 1 , wherein
the semiconductor channel comprises an angled structure; and a third diameter of the semiconductor channel at a bottom portion of the channel structure below the angled structure is smaller than a fourth diameter of the semiconductor channel at an upper portion of the channel structure above the angled structure.

9 . The memory device of claim 8 , wherein the semiconductor channel below the angled structure comprises a solid pillar structure.

10 . The memory device of claim 8 , wherein the semiconductor channel above the angled structure comprises a hollow structure.

11 . The memory device of claim 1 , further comprising a doped polysilicon layer disposed under the polysilicon layer, wherein the polysilicon layer is between the stack structure and the doped polysilicon layer.

12 . The memory device of claim 11 , wherein the polysilicon layer surrounds a bottom portion of the channel structure, and the doped polysilicon layer is disposed under the bottom portion of the channel structure.

13 . A memory device, comprising:
a stack structure comprising interleaved first conductive layers and first dielectric layers; and a channel structure extending through the stack structure along a first direction, the channel structure comprising a semiconductor channel, a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer; and a polysilicon layer under the stack structure and comprising a protruding portion which is in contact with the semiconductor channel.

14 . The memory device of claim 13 , wherein the tunneling layer, the storage layer, and the blocking layer are in direct contact with the protruding portion.

15 . The memory device of claim 13 , further comprising a gate line slit extending through the stack structure along the first direction and in contact with the polysilicon layer.

16 . The memory device of claim 13 , further comprising a first contact pad in contact with the polysilicon layer, wherein the polysilicon layer is between the stack structure and the first contact pad in the first direction.

17 . The memory device of claim 13 , further comprising:
a contact structure over the polysilicon layer and extending along the first direction in or out of the stack structure; and a second contact pad extending through the polysilicon layer along the first direction and in contact with the contact structure.

18 . The memory device of claim 13 , wherein a first thickness of the blocking layer at a bottom portion of the channel structure is larger than a second thickness of the blocking layer at an upper portion of the channel structure.

19 . The memory device of claim 18 , further comprising a dielectric core in the semiconductor channel,
wherein the dielectric core is surrounded by the semiconductor channel at the bottom portion of the channel structure, and a first diameter of the dielectric core at the bottom portion of the channel structure is smaller than a second diameter of the dielectric core at the upper portion of the channel structure.

20 . A method for forming a memory device, comprising:
forming a stack structure comprising interleaved first conductive layers and first dielectric layers; and forming a channel structure extending through the stack structure along a first direction, the channel structure comprising a semiconductor channel, a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer; and forming a polysilicon layer under the stack structure and in contact with the semiconductor channel, wherein the tunneling layer, the storage layer, and the blocking layer are in direct contact with the polysilicon layer.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Wu Linchun
• Zhang Kun
• Zhou Wenxi
• Xia Zhiliang
• Xie Wei
• Wang Di
• Wang Bingguo
• Huo Zongliang

Classifications

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B41/50

  characterised by the boundary region between the core region and the peripheral circuit region · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title