Logic-uppermost semiconductor device assemblies with reconstituted wafers and multi-reticle dies coupled by reticle-bridging conductors

Patent metadata

Field	Value
Publication number	US-2026041008-A1
Application number	US-202519281140-A
Country	US
Kind code	A1
Filing date	Jul 25, 2025
Priority date	Jul 31, 2024
Publication date	Feb 5, 2026
Grant date	—

Abstract

A semiconductor device assembly includes a plurality of stacks of semiconductor devices horizontally spaced apart by a gap fill material, each including multiple devices coupled by TSVs to external package contacts through an RDL, and a device connection layer formed over the stacks and including a first plurality of contacts coupled to the TSVs, a second plurality of contacts facing away from the TSVs, a first plurality of conductors coupling contacts of the first plurality to corresponding contacts of the second plurality, and a second plurality of conductors coupling contacts of the second plurality to other contacts of the second plurality. The assembly further includes a multi-reticle semiconductor device over the device connection layer and including a plurality of circuit regions horizontally spaced apart from one another by a reticle-edge region absent any electrical conductors. The second plurality of conductors in the device connection layer operably interconnect the circuit regions.

First claim

What is claimed is:

1 . A semiconductor device assembly, comprising:
a plurality of stacks of semiconductor devices horizontally spaced apart by a gap fill material, each stack of the plurality including multiple vertically-aligned semiconductor devices operably coupled by through-silicon vias (TSVs) to a plurality of external package contacts through a redistribution layer (RDL); a device connection layer formed over the plurality of stacks of semiconductor devices and including a first plurality of contacts facing and coupled to the TSVs, a second plurality of contacts facing away from the TSVs, a first plurality of conductors operably coupling individual contacts of the first plurality to corresponding individual contacts of the second plurality, and a second plurality of conductors operably coupling individual contacts of the second plurality to other individual contacts of the second plurality; and a multi-reticle semiconductor device disposed over the device connection layer, the multi-reticle semiconductor device including a plurality of circuit regions horizontally spaced apart from one another by a reticle-edge region absent any electrical conductors, wherein the second plurality of conductors in the device connection layer operably interconnect the plurality of circuit regions.

2 . The semiconductor device assembly of claim 1 , wherein the gap fill material comprises silicon oxide, silicon nitride, a mold material, or a combination thereof.

3 . The semiconductor device assembly of claim 1 , wherein the plurality of circuit regions of the multi-reticle semiconductor device is disposed face the device connection layer.

4 . The semiconductor device assembly of claim 1 , wherein the second plurality of conductors extends horizontally under the reticle-edge region of the multi-reticle semiconductor device.

5 . The semiconductor device assembly of claim 1 , wherein:
the multi-reticle semiconductor device includes a first bonding surface including a first planar dielectric surface and a third plurality of contacts, and the device connection layer includes a second bonding surface including a second planar dielectric surface and the second plurality of contacts, and the first bonding surface and the second bonding surface are hybrid-bonded to one another such that the first planar dielectric surface and the second planar dielectric surface are bonded by a dielectric-dielectric bond and such that each of the second plurality of contact pads is bonded to a corresponding one of the third plurality of contact pads by a metal-metal bond exclusive of any solder.

6 . The semiconductor device assembly of claim 1 , further comprising a plurality of through-gap fill vias extending from the device connection layer to the RDL, each of the through-gap fill vias comprising a continuously tapering body of conductive metal.

7 . The semiconductor device assembly of claim 6 , wherein each through-gap fill via of the plurality of through-gap fill vias electrically couples the multi-reticle semiconductor device to an external package contact of the plurality of external package contacts exclusive of connection to any circuitry of the plurality of stacks of semiconductor devices.

8 . The semiconductor device assembly of claim 1 , further comprising a plurality of silicon slugs including a continuous body of silicon extending from the device connection layer to the RDL, each of the silicon slugs including a TSV comprising a continuously tapering body of conductive metal that electrically couples the multi-reticle semiconductor device to an external package contact of the plurality of external package contacts.

9 . The semiconductor device assembly of claim 1 , wherein a region of the gap fill material extending between the device connection layer and the RDL is seamless.

10 . A semiconductor device assembly, comprising:
a redistribution layer (RDL) including:
an external surface including a plurality of external contacts,
an internal surface including a plurality of internal contacts, and
a plurality of conductors operably coupling individual ones of the plurality of internal contacts to individual ones of the plurality of external contacts;
a device connection layer including:
a first surface having a first plurality of contact pads,
a second surface opposite the first surface and having a second plurality of contact pads,
a first plurality of conductive structures electrically coupling each of the first plurality of contact pads to a corresponding contact pad of the second plurality of contact pads, and
a second plurality of conductive structures electrically coupling each of a first subset of the second plurality of contact pads to a corresponding contact pad of a second subset of the second plurality of contact pads; and
a plurality of stacks of semiconductor devices disposed between the RDL and the device connection layer, horizontally spaced apart by a gap fill material, and electrically coupling individual ones of the plurality of internal contacts to individual ones of the first plurality of contact pads through TSVs disposed in the plurality of stacks.

11 . The semiconductor device assembly of claim 10 , wherein a region of the gap fill material extending between the device connection layer and the RDL is seamless.

12 . The semiconductor device assembly of claim 10 , wherein the gap fill material comprises silicon oxide, silicon nitride, a mold material, or a combination thereof.

13 . The semiconductor device assembly of claim 10 , further comprising a plurality of through gap fill vias extending from the RDL to the device connection layer, each of the through-gap fill vias comprising a continuously tapering body of conductive metal.

14 . The semiconductor device assembly of claim 10 , further comprising a plurality of silicon slugs including a continuous body of silicon extending from the device connection layer to the RDL, each of the silicon slugs including a TSV comprising a continuously tapering body of conductive metal that electrically couples the multi-reticle semiconductor device to an external package contact of the plurality of external package contacts.

15 . A method of making a semiconductor device assembly, comprising:
providing a semiconductor device sub-assembly, the semiconductor device sub-assembly including:
a redistribution layer (RDL) including an external surface including a plurality of external contacts, an internal surface including a plurality of internal contacts, and a plurality of conductors operably coupling individual ones of the plurality of internal contacts to individual ones of the plurality of external contacts;
a device connection layer including a first surface having a first plurality of contact pads, a second surface opposite the first surface and having a second plurality of contact pads, a first plurality of conductive structures electrically coupling each of the first plurality of contact pads to a corresponding contact pad of the second plurality of contact pads, and a second plurality of conductive structures electrically coupling each of a first subset of the second plurality of contact pads to a corresponding contact pad of a second subset of the second plurality of contact pads; and
a plurality of stacks of semiconductor devices disposed between the RDL and the device connection layer, horizontally spaced apart by a gap fill material, and electrically coupling individual ones of the plurality of internal contacts to individual ones of the first plurality of contact pads through TSVs disposed in the plurality of stacks; and
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Assignees

• Micron Technology Inc

Inventors

• Bhushan Bharat
• Parekh Kunal R
• Singh Akshay N
• Zaleski Mark
• Akel Ameen D
• Street Bret K

Classifications

• H01L2225/06541

  Electricity · mapped topic

• H01L2224/80896

  Electricity · mapped topic

• H01L2224/80895

  Electricity · mapped topic

• H01L2224/24146

  Electricity · mapped topic

• H01L2224/24137

  Electricity · mapped topic