Memory die bonding in stacked semiconductor systems

Patent metadata

Field	Value
Publication number	US-2026040582-A1
Application number	US-202519278689-A
Country	US
Kind code	A1
Filing date	Jul 23, 2025
Priority date	Jul 31, 2024
Publication date	Feb 5, 2026
Grant date	—

Abstract

Methods, systems, and devices for memory die bonding in stacked semiconductor systems are described. A semiconductor device may be formed to include a stack of memory dies. Each memory die of the stack may be bonded with at least one other memory die of the stack. The semiconductor device may include a dielectric material in contact with a portion of a first memory die of the stack, with the dielectric material extending beyond at least one lateral boundary of the first memory die of the stack. The semiconductor device may also include one or more molding materials formed over the stack of memory dies and over the dielectric material, with the one or more molding materials spanning a lateral dimension of the dielectric material and in contact with a portion of at least one memory die of the stack.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a stack of memory dies, wherein each memory die of the stack is bonded with at least one other memory die of the stack; a dielectric material in contact with a portion of a first memory die of the stack, the dielectric material extending beyond at least one lateral boundary of the first memory die of the stack; and one or more molding materials formed over the stack of memory dies and over the dielectric material, the one or more molding materials spanning a lateral dimension of the dielectric material and in contact with a portion of at least one memory die of the stack.

2 . The semiconductor device of claim 1 , further comprising:
one or more second molding materials formed over the one or more molding materials.

3 . The semiconductor device of claim 1 , further comprising:
a plurality of contacts formed at a first surface of the first memory die of the stack, the plurality of contacts for making electrical connections with one or more other semiconductor dies.

4 . The semiconductor device of claim 3 , wherein the first memory die is bonded with a second memory die of the stack at a second surface of the first memory die that is opposite the first surface.

5 . The semiconductor device of claim 1 , further comprising:
a substrate bonded with a second memory die of the stack of memory dies, the second memory die located at an opposite end of the semiconductor device as the first memory die.

6 . The semiconductor device of claim 1 , wherein each memory die of the stack is bonded with at least one other memory die of the stack by a first plurality of contacts.

7 . The semiconductor device of claim 1 , wherein the stack of memory dies comprises three or more memory dies.

8 . A method for manufacturing a semiconductor device, comprising:
bonding a respective first surface of a set of first memory dies to a carrier; forming a dielectric material between and over each of the first memory dies and over the carrier, the dielectric material extending beyond respective lateral boundaries of each first memory die; forming one or more stacks of memory dies above the set of first memory dies by bonding a set of second memory dies to respective second surfaces of the set of first memory dies opposite the respective first surfaces; forming, after bonding the set of second memory dies, one or more molding materials between and over each stack of memory dies and over the dielectric material, the one or more molding materials spanning a lateral dimension of the dielectric material and in contact with a portion of at least one second memory die; removing the carrier to expose the respective first surfaces of the first memory dies, the respective first surfaces comprising a plurality of contacts for making electrical connections with one or more other semiconductor dies; and removing a portion of the one or more molding materials and a portion of the dielectric material, wherein each stack of memory dies is separated from other stacks of memory dies based at least in part on removing the portion of the one or more molding materials and the portion of the dielectric material.

9 . The method of claim 8 , further comprising:
bonding, after removing the portion of the one or more molding materials and the portion of the dielectric material, a first stack of the one or more stacks of memory dies with a substrate of a semiconductor die; and forming one or more second molding materials over the one or more molding materials, the one or more second molding materials spanning a lateral dimension of the substrate and in contact with a portion of the dielectric material.

10 . The method of claim 8 , further comprising:
forming, after removing the carrier and before removing the portion of the one or more molding materials and the portion of the dielectric material, the plurality of contacts of the respective first surfaces with one or more conductive materials.

11 . The method of claim 8 , further comprising:
forming, after forming the dielectric material, a plurality of second contacts of the respective second surfaces with one or more conductive materials, wherein bonding the set of second memory dies to the respective second surfaces is based at least in part on forming the plurality of second contacts.

12 . The method of claim 11 , wherein bonding the set of second memory dies to the respective second surfaces comprises:
bonding the plurality of second contacts with a plurality of third contacts formed at a respective first surfaces of the set of second memory dies.

13 . The method of claim 8 , further comprising:
bonding, after forming the one or more molding materials, respective second surfaces of the set of second memory dies with a substrate to extend a height dimension of the semiconductor device.

14 . The method of claim 8 , further comprising:
determining that each first memory die of the set of first memory dies satisfies an evaluation procedure prior to bonding on the carrier.

15 . A semiconductor device, comprising:
a first stack comprising a first plurality of memory dies, each memory die of the first stack bonded with at least one other memory die in the first stack; a first dielectric material in contact with a portion of a first memory die of the first stack, the first dielectric material extending beyond each lateral boundary of the first memory die of the stack; a second stack comprising a second plurality of memory dies, each memory die of the second stack bonded with at least one other memory die in the second stack, a first memory die of the second stack being bonded with a second memory die of the first stack; and a second dielectric material in contact with a portion of the first memory die of the second stack, the second dielectric material extending beyond each lateral boundary of the first memory die of the second stack.

16 . The semiconductor device of claim 15 , further comprising:
one or more first molding materials formed over the first stack, the one or more first molding materials spanning a lateral dimension of the first dielectric material and in contact with a portion of at least one memory die of the first stack.

17 . The semiconductor device of claim 16 , further comprising:
one or more second molding materials formed over the second stack, the one or more second molding materials spanning a lateral dimension of the second dielectric material and in contact with a portion of at least one memory die of the second stack.

18 . The semiconductor device of claim 17 , further comprising:
one or more third molding materials formed between and over the first stack and the second stack, the one or more third molding materials in contact with the one or more first molding materials and the one or more second molding materials and extending beyond a lateral dimension of the first dielectric material and the second dielectric material.

19 . The semiconductor device of claim 16 , further comprising:
a third dielectric material formed over a surface of the second memory die of the first stack and over the one or more first molding materials, the third dielectric material spanning a lateral dimension of the one or more first molding materials.

20 . The semiconductor device of claim 15 , further comprising:
a plurality of contacts for making electrical connections, the plurality of contacts formed at a surface of the second memory die of the first stack, wherein a bond between the sec

Assignees

• Micron Technology Inc

Inventors

• Huang Sui Chi
• Singh Akshay N
• Street Bret K

Classifications

• H01L2225/06586

  Electricity · mapped topic

• H01L2225/06541

  Electricity · mapped topic

• H01L2225/06513

  Electricity · mapped topic

• H01L25/50

  Electricity · mapped topic

• H01L25/18

  Electricity · mapped topic