Memory Circuitry Comprising Strings of Memory Cells and Method Used in Forming a Memory Array Comprising Strings of Memory Cells

Patent metadata

Field	Value
Publication number	US-2026040541-A1
Application number	US-202519356779-A
Country	US
Kind code	A1
Filing date	Oct 13, 2025
Priority date	Feb 4, 2022
Publication date	Feb 5, 2026
Grant date	—

Abstract

Memory circuitry comprising strings of memory cells comprising memory blocks individually comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers of the memory blocks extend from the memory-array region into a stair-step region. Individual of the memory blocks in the stair-step region comprise a flight of operative stairs. Individual of the operative stairs comprise one of the conductive tiers. At least some immediately-laterally-adjacent of the individual memory blocks in the stair-step region have their flights of operative stairs laterally-separated by a stack comprising two vertically-alternating different-composition insulative materials. Other embodiments, including method, are disclosed.

First claim

1 : A method used in forming a memory array comprising strings of memory cells, comprising:
forming a stack comprising vertically-alternating first tiers and second tiers comprising different composition first insulative material and second insulative material, respectively, on a substrate; the stack comprising memory-block regions extending from a memory-array region into a stair-step region along a first direction; forming a stair-step structure comprising the first and second tiers in the stair-step region across and that spans between two immediately-adjacent of the memory-block regions along a second direction; forming trenches along the first direction that are individually laterally between immediately-adjacent of the memory blocks in the memory-array region, two of the trenches in the first direction extending completely across the stair-step structure laterally-outward of opposing sides of the stair-step structure, one of the trenches being laterally between the two trenches and not extending completely across the stair-step structure in the first direction; etching the first insulative material selectively relative to the second insulative material through the two and one trenches to leave a stack of the first and second insulative materials in the stair-step structure that is laterally-spaced from the two trenches; after the etching, forming conductive material in the first tiers through the one and two trenches; forming a wall in individual of the one and two trenches; and forming channel material strings that extend through the first tiers and the second tiers in the memory-block regions.

2 : The method of claim 1 wherein the wall in the one trench includes an end portion that extends into the stack of the first and second insulative materials.

3 : The method of claim 2 wherein the wall in the one trench is horizontally-longitudinally-elongated, the end portion being everywhere horizontally longitudinally-spaced from where all of the channel-material strings extend through the first tiers and the second tiers, the end portion having a maximum lateral width that is greater than a maximum lateral width of that portion of the wall in the one trench that is not horizontally-longitudinally-spaced from where all of the channel-material strings extend through the first tiers and the second tiers.

4 : The method of claim 2 wherein the wall in the one trench is horizontally-longitudinally-elongated, the end portion being everywhere horizontally longitudinally-spaced from where all of the channel-material strings extend through the first tiers and the second tiers, the end portion and that portion of the wall in the one trench that is not horizontally-longitudinally-spaced from where all of the channel-material strings extend through the first tiers and the second tiers being formed at different times relative one another.

5 : The method of claim 4 wherein the end portion is formed before forming that portion of the wall in the one trench that is not horizontally longitudinally-spaced from where all of the channel-material strings extend through the first tiers and the second tiers.

6 : The method of claim 5 wherein the stair-step structure and the end portion are formed using a common masking step.

7 : The method of claim 5 wherein the stair-step structure and the end portion are not formed using a common masking step.

8 : The method of claim 7 comprising forming stairs of the stair-step structure before forming the end portion.

9 : The method of claim 1 wherein the stair-step structure after the etching forms the stack of the first and second insulative materials in the stair-step structure that is laterally-spaced from the two trenches to comprise a flight of inoperative stairs.

10 : A method of forming memory circuitry, comprising:
forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers, strings of memory cells extending through the insulative tiers and the conductive tiers in a memory array region, the insulative tiers and the conductive tiers of the memory blocks extending from the memory array region into a stair step region; individual of the memory blocks in the stair-step region comprising a flight of operative stairs, individual of the operative stairs comprising one of the conductive tiers; at least some adjacent of the individual memory blocks in the stair step region having flights of operative stairs separated by a stack comprising two vertically alternating insulative materials; and forming walls that are individually between the adjacent memory blocks in the memory array region, the walls individually comprising an end portion that is in the stack comprising the two vertically alternating insulative materials.

11 : The method of claim 10 wherein the walls are comprised by a first set of walls and further comprising forming a second set of walls, the walls of the first and second sets being individually laterally between the adjacent memory blocks, the walls of the second set being horizontally longer than the walls of the first set.

12 : The method of claim 11 wherein individual of the walls of the first set laterally alternate with individual of the walls of the second set.

13 : A method of forming memory circuitry, comprising:
forming two memory-array regions having a stair-step region there-between; forming memory blocks in each of the two memory-array regions that individually comprise a vertical stack of alternating insulative tiers and conductive tiers; forming channel material strings of memory cells extending through the insulative tiers and the conductive tiers in the memory blocks in the two memory-array regions; and forming walls that are individually laterally between adjacent of the memory blocks in the two memory-array regions, the walls comprising a first set of the walls that extend from one of the two memory array regions into the other of the two memory-array regions across the stair-step region, the walls comprising a second set of walls that extend from one of the two memory array regions only partially into the stair-step region.

14 : The method of claim 13 wherein,
individual of the memory blocks in the stair-step region comprise a flight of operative stairs, individual of the operative stairs comprising one of the conductive tiers; and
at least some adjacent of the individual memory blocks in the stair-step region having their flights of operative stairs laterally separated by a stack comprising two vertically-alternating insulative materials.

15 : The method of claim 13 wherein:
individual of the memory blocks in the stair-step region comprise a flight of operative stairs, individual of the operative stairs comprising one of the conductive tiers; and
at least some adjacent of the individual memory blocks in the stair-step region having flights of operative stairs laterally-separated by a flight of inoperative stairs.

16 : The method of claim 13 wherein the walls of the second set individually comprise an end portion that is in a stack comprising two vertically alternating insulative materials.

Assignees

• Micron Technology Inc

Inventors

• Xu Lifang
• Hill Richard J
• Fukuzumi Yoshiaki
• Tessariol Paolo

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title

• H10B41/10

  characterised by the top-view layout · CPC title

• H10B12/0387

  Making the trench · CPC title