Techniques to form bridges between blocks of memory cells

Patent metadata

Field	Value
Publication number	US-2026020238-A1
Application number	US-202519264300-A
Country	US
Kind code	A1
Filing date	Jul 9, 2025
Priority date	Jul 15, 2024
Publication date	Jan 15, 2026
Grant date	—

Abstract

Methods, systems, and devices for techniques to form bridges between blocks of memory cells are described. A memory system may include a partial set of oxide bridges extending across a slot region between blocks of memory cells. For example, blocks of a memory system may include alternating layers of an oxide material and a conductive material. The blocks may be separated by a slot region. A first subset of the layers of oxide material may extend across the slot region to form oxide bridges, which may provide structural stability to the memory system. A second subset of the oxide layers, along with the conductive layers, may not extend across the slot region, which may support forming a trench during a manufacturing process of the memory system. Such a trench may provide an access point to the stack of layers to remove nitride material and deposit the conductive material.

First claim

What is claimed is:

1 . An apparatus, comprising:
a first block of memory cells comprising a first stack of layers, the first stack of layers comprising a first plurality of layers of a conductive material separated by a first plurality of layers of one or more dielectric materials, each memory cell of the first block of memory cells coupled between a respective layer of the conductive material and a respective pillar of a first plurality of pillars extending through the first stack of layers; a second block of memory cells comprising a second stack of layers, the second stack of layers comprising a second plurality of layers of the conductive material separated by a second plurality of layers of the one or more dielectric materials, each memory cell of the second block of memory cells coupled between a respective layer of the conductive material and a respective pillar of a second plurality of pillars extending through the second stack of layers; and a slot region separating the first stack of layers of the first block of memory cells from the second stack of layers of the second block of memory cells, wherein respective layers of the conductive material of the first plurality of layers are separated from corresponding layers of the conductive material of the second plurality of layers by the slot region, wherein a first subset of layers of the one or more dielectric materials of the first plurality of layers of the one or more dielectric materials are separated from corresponding layers of the one or more dielectric materials of the second plurality of layers by the slot region, and wherein a second subset of layers of the one or more dielectric materials of the first plurality of layers extend across the slot region to contact corresponding layers of the one or more dielectric materials of the second plurality of layers.

2 . The apparatus of claim 1 , wherein the one or more dielectric materials are a same dielectric material for each of the first subset of layers and the second subset of layers.

3 . The apparatus of claim 1 , wherein the first subset of layers of the one or more dielectric materials are a first dielectric material and the second subset of layers of the one or more dielectric materials are a second dielectric material different than the first dielectric material.

4 . The apparatus of claim 3 , wherein the first dielectric material is an oxide and the second dielectric material comprises the oxide doped with a dopant material.

5 . The apparatus of claim 4 , wherein the dopant material is carbon.

6 . The apparatus of claim 1 , wherein:
the second subset of layers comprises a plurality of groups of one or more layers, and each group of the second subset of layers is separated from other groups of the second subset of layers by one or more layers of the first subset of layers.

7 . The apparatus of claim 6 , wherein:
the first and second stacks of layers comprise a plurality of decks of layers, and the plurality of groups of one or more layers comprise one or more layers at corresponding locations in each deck of the plurality of decks of layers.

8 . The apparatus of claim 1 , wherein the second subset of layers are positioned above the first subset of layers relative to a substrate.

9 . A method, comprising:
forming a stack of layers along a first direction above a substrate based at least in part on forming alternating layers of a first material and a second material; forming a first set of cavities and a second set of cavities in the stack of layers; forming a film on first portions of the first material for a first subset of layers of the first material of the stack of layers; removing portions of the first material via the first set of cavities to merge adjacent cavities of the first set of cavities, wherein the removing is selective to the first material for a second subset of layers of the first material of the stack of layers exclusive of the first subset of layers based at least in part on the film formed on the first portions of the first material for the first subset of layers, and wherein adjacent cavities are merged for the second subset of layers of the first material based at least in part on the removal of the portions of the first material; and replacing, via the first set of cavities or the second set of cavities, at least a portion of the second material of the stack of layers with a conductive material associated with accessing one or more memory cells.

10 . The method of claim 9 , further comprising:
filling each cavity of the first set of cavities and each cavity of the second set of cavities with a sacrificial material after forming the first set of cavities and the second set of cavities.

11 . The method of claim 10 , further comprising:
exhuming the sacrificial material from the second set of cavities; and filling each cavity of the second set of cavities with a third material associated with accessing the one or more memory cells, wherein the third material is a conductive material or a semiconductor material.

12 . The method of claim 11 , further comprising:
forming a memory material in portions of at least a subset of layers of the second material of the stack of layers after exhuming the sacrificial material from the second set of cavities, wherein each cavity of the second set of cavities are filled with the third material after forming the memory material.

13 . The method of claim 11 , further comprising:
exhuming the sacrificial material from the first set of cavities after exhuming the sacrificial material from the second set of cavities, wherein forming the film on the first portions is performed after exhuming the sacrificial material from the first set of cavities.

14 . The method of claim 9 , wherein forming the first set of cavities and second set of cavities comprises removing portions of the second material and second portions of the first material using a dry etch.

15 . The method of claim 9 , wherein removing the first material via the first set of cavities comprises removing third portions of the first material using a wet etch selective to the first material.

16 . The method of claim 9 , wherein the film comprises a carbon material.

17 . The method of claim 9 , further comprising:
removing the film using an etch selective to the film.

18 . A method, comprising:
forming a stack of first layers arranged along a first direction, the stack of first layers comprising alternating layers of a first material and a second material; forming a stack of second layers above the stack of first layers along the first direction, wherein the stack of second layers comprises alternating layers of a third material and the second material, the third material different than the first material and the second material; forming a first set of cavities and a second set of cavities in the stack of first layers and the stack of second layers; removing portions of the first material in the stack of first layers and the stack of second layers via the first set of cavities to merge adjacent cavities of the first set of cavities, wherein the first material is removed at a faster rate than the third material, and wherein removing the portions of the first material merges adjacent cavities for layers of the first material in the stack of first layers; and replacing, via the first set of cavities, at least a portion of the second material of the stack of first layers and the stack of second layers with a conductive material associated with accessing one or more memory cells

Assignees

• Micron Technology Inc

Inventors

• Gupta Sidhartha
• Hill Richard J
• King Matthew J

Classifications

• H10B41/10

  characterised by the top-view layout · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title