Digital duty cycle corrector circuit

Patent metadata

Field	Value
Publication number	US-2026005680-A1
Application number	US-202418756990-A
Country	US
Kind code	A1
Filing date	Jun 27, 2024
Priority date	Jun 27, 2024
Publication date	Jan 1, 2026
Grant date	—

Abstract

A digital duty cycle corrector circuit is provided. The duty cycle corrector circuit includes a control circuit having a first transistor and a second transistor connected at a first node and configured to adjust a duty cycle of an input clock received at the first node and provide a duty adjusted output clock at a second node. A single to differential circuit is connected to the control circuit at the second node. The single to differential circuit generates a first output clock and a second output clock from the duty adjusted output clock. A feedback circuit configured to provide the duty adjusting output clock to a gate of each of the first transistor and the second transistor.

First claim

What is claimed is:

1 . A digital duty cycle corrector circuit, comprising:
a control circuit comprising a first transistor and a second transistor, wherein:
a source/drain of the first transistor is connected to a first trim circuit, wherein the first trim circuit provides a first voltage at the source/drain of the first transistor,
a drain/source of the first transistor is connected to a drain/source of the second transistor at a first node,
a source/drain of the second transistor is connected to a second trim circuit, wherein the second trim circuit provides a second voltage at the source/drain of the second transistor,
the control circuit is configured to adjust a duty cycle of an input clock received at the first node and provide a duty adjusted output clock at a second node, and
the control circuit further comprises a feedback circuit that connects the second node to a gate of each of the first transistor and the second transistor; and
a single to differential circuit connected to the control circuit, wherein the single to differential circuit is configured to generate a first output clock and a second output clock from the duty adjusted output clock.

2 . The digital duty cycle corrector circuit of claim 1 , wherein the first trim circuit comprises a first plurality of transistors, wherein each of the first plurality of transistors are connected in parallel to each other between a supply voltage node and the source/drain of the first transistor.

3 . The digital duty cycle corrector circuit of claim 1 , wherein the second trim circuit comprises a second plurality of transistors, wherein each of the second plurality of transistors are connected in parallel to each other between the source/drain of the second transistor and a ground voltage node.

4 . The digital duty cycle corrector circuit of claim 1 , wherein the feedback node comprises the second node.

5 . The digital duty cycle corrector circuit of claim 1 , wherein the feedback node comprises another node in the single to differential circuit that in a same phase as the second node.

6 . The digital duty cycle corrector circuit of claim 1 , wherein an inverted clock signal is received at the first node.

7 . The digital duty cycle corrector circuit of claim 1 , wherein the feedback node comprises another node on a first branch of the single to differential circuit that in a same phase as the second node.

8 . The digital duty cycle corrector circuit of claim 1 , wherein the feedback node comprises another node on a second branch the single to differential circuit that in a same phase as the second node.

9 . The digital duty cycle corrector circuit of claim 1 , wherein the control circuit further comprises an invertor connected between the first node and the second node.

10 . A digital duty cycle corrector circuit, comprising:
a control circuit comprising a first transistor and a second transistor connected at a first node and configured to adjust a duty cycle of an input clock received at the first node and provide a duty adjusted output clock at a second node; a single to differential circuit connected to the control circuit at the second node, wherein the single to differential circuit is configured to generate a first output clock and a second output clock from the duty adjusted output clock; and a feedback circuit configured to provide the duty adjusting output clock to a gate of each of the first transistor and the second transistor.

11 . The digital duty cycle corrector circuit of claim 10 , wherein the control circuit further comprising:
a first trim circuit connected to a source/drain of the first transistor, wherein the first trim circuit provides a first voltage at the source/drain of the first transistor; and a second trim circuit connected to a source/drain of the second transistor, wherein the second trim circuit provides a second voltage at the source/drain of the second transistor, and wherein a drain/source of the first transistor is connected to a drain/source of the second transistor at the first node.

12 . The digital duty cycle corrector circuit of claim 10 , wherein the feedback circuit connects the second node to the gate of each of the first transistor and the second transistor.

13 . The digital duty cycle corrector circuit of claim 10 , wherein the feedback circuit connects another node in the single to differential circuit that in a same phase as the second node to the gate of each of the first transistor and the second transistor.

14 . The digital duty cycle corrector circuit of claim 10 , wherein the feedback circuit connects another node on a first branch of the single to differential circuit that in a same phase as the second node to the gate of each of the first transistor and the second transistor.

15 . The digital duty cycle corrector circuit of claim 10 , wherein the feedback circuit connects another node on a second the single to differential circuit that in a same phase as the second node to the gate of each of the first transistor and the second transistor.

16 . The digital duty cycle corrector circuit of claim 10 , wherein the control circuit further comprises an invertor connected between the first node and the second node.

17 . A method of adjusting a duty cycle of an input clock, the method comprising:
receiving an input clock at a first node of a control circuit comprising a first transistor and a second transistor connected at the first node; adjusting a duty cycle of the input clock based on a first trim code and a second trim code; providing a duty adjusted output clock at a second node of the control circuit; and providing the duty adjusted output clock as feedback at a gate of each of the first transistor and the second transistor of the control circuit.

18 . The method of claim 17 , further comprising:
generating, by a single to differential circuit connected to the control circuit at the second node, a first output clock and a second output clock from the duty adjusted output clock.

19 . The method of claim 18 , wherein providing the duty adjusted output clock as feedback at the gate of each of the first transistor and the second transistor of the control circuit comprises providing the duty adjusted output clock from another node in single to differential circuit as feedback at the gate of each of the first transistor and the second transistor of the control circuit.

20 . The method of claim 17 , wherein providing the duty adjusted output clock as feedback at the gate of each of the first transistor and the second transistor of the control circuit comprises providing the duty adjusted output clock from the second node as feedback at the gate of each of the first transistor and the second transistor of the control circuit.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Li Chang-Yi

Classifications

• H03K3/017

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03K5/135

  by the use of time reference signals, e.g. clock signals · CPC title

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title