CMOS analog circuits having a triode-based active load

Patent metadata

Field	Value
Publication number	US-11177984-B1
Application number	US-202016889573-A
Country	US
Kind code	B1
Filing date	Jun 1, 2020
Priority date	Jun 1, 2020
Publication date	Nov 16, 2021
Grant date	Nov 16, 2021

Abstract

A continuous time linear equalizer (CTLE) is disclosed. The CTLE may include a first cell configured to buffer and invert an input signal and generate a first intermediate signal, a second cell configured to buffer and invert the input signal and generate a second intermediate signal, and a first frequency section configured to selectively buffer and invert a first range of frequencies of the second intermediate signal. The first frequency section may include a first tunable resistor configured to provide a first resistance and a third cell coupled to the first tunable resistor configured to generate a third intermediate signal based on the first resistance.

First claim

What is claimed is:

1. A continuous time linear equalizer (CTLE), comprising:
a first cell configured to generate a first intermediate signal by buffering and inverting an input signal;
a second cell configured to generate a second intermediate signal by buffering and inverting the input signal;
a first frequency section configured to selectively generate a third intermediate signal based at least in part on the second intermediate signal, the first frequency section including:
a first tunable resistor configured to provide a first resistance, the first tunable resistor comprising a first PMOS transistor and a first NMOS transistor, wherein a drain of the first PMOS transistor is coupled to a drain of the first NMOS transistor and a source of the first PMOS transistor is coupled to a source of the first NMOS transistor, the drains of the first PMOS and NMOS transistors being configured to receive the second intermediate signal; and
a third cell configured to generate the third intermediate signal by buffering and inverting the second intermediate signal based on the first resistance, wherein the first resistance determines, at least in part, a first range of frequencies buffered by the third cell; and
an output configured to provide an equalized output signal based at least in part on a sum of the first intermediate signal and the third intermediate signal;
wherein the sources of the first PMOS and NMOS transistors are coupled to an input of the third cell.

2. The CTLE of claim 1 , wherein the first PMOS transistor and the first NMOS transistor are configured to operate in a triode mode.

3. The CTLE of claim 1 , further comprising:
a digital-to-analog converter (DAC) coupled to the first PMOS transistor and the first NMOS transistor, the DAC being configured to modify the first resistance.

4. The CTLE of claim 3 , wherein the DAC comprises a first output coupled to a gate of the first PMOS transistor and a second output coupled to a gate of the first NMOS transistor.

5. The CTLE of claim 3 , further comprising:
a second frequency section configured to selectively generate a fourth intermediate signal based at least in part on the second intermediate signal, the second frequency section including:
a second tunable resistor configured to provide a second resistance; and
a fourth cell configured to generate the fourth intermediate signal by buffering and inverting the second intermediate signal based on the second resistance, wherein the second resistance determines, at least in part, a second range of frequencies buffered by the fourth cell.

6. The CTLE of claim 5 , wherein the equalized output signal is based on a sum of the first intermediate signal and the fourth intermediate signal.

7. The CTLE of claim 5 , wherein the second tunable resistor comprises:
a second PMOS transistor and a second NMOS transistor, wherein a drain of the second PMOS transistor is coupled to a drain of the second NMOS transistor and a source of the second PMOS transistor is coupled to a source of the second NMOS transistor, the drains of the second PMOS and NMOS transistors being configured to receive the second intermediate signal, and the sources of the second PMOS and NMOS transistors being further coupled to an input of the fourth cell.

8. The CTLE of claim 7 , wherein a channel area of each of the second PMOS and NMOS transistors is less than a channel area of each of the first PMOS and NMOS transistors.

9. The CTLE of claim 1 , further comprising an active load configured to extend a bandwidth of the CTLE.

10. The CTLE of claim 9 , wherein the active load is further configured to provide an inductive-resistive load to the first cell and the second cell based on a transconductance of the first PMOS transistor and the first NMOS transistor.

11. A method for operating a continuous time linear equalizer, comprising:
generating a first intermediate signal by buffering and inverting an analog signal;
generating a second intermediate signal by buffering and inverting the analog signal and coupling the second intermediate signal to a first cell via a first tunable resistor including a first PMOS transistor and a first NMOS transistor;
generating a third intermediate signal by buffering and inverting the second intermediate signal based on a first resistance, wherein the first resistance determines, at least in part, a first range of frequencies, and wherein the first resistance is provided by the first tunable resistor;
and summing the first intermediate signal with the third intermediate signal to generate an equalized signal.

12. The method of claim 11 , wherein a drain of the first PMOS transistor is coupled to a drain of the first NMOS transistor and a source of the first PMOS transistor is coupled to a source of the first NMOS transistor, the drains of the first PMOS and NMOS transistors being configured to receive the second intermediate signal, and the sources of the first PMOS and NMOS transistors being further coupled to an input of the first cell.

13. The method of claim 11 , wherein the first PMOS transistor and the first NMOS transistor operate in a triode mode.

14. The method of claim 11 , wherein the generating of the third intermediate signal comprises adjusting the first tunable resistor to determine the first range of frequencies.

15. The method of claim 14 , further comprising:
generating, by a digital-to-analog converter (DAC) one or more voltages to adjust the first tunable resistor.

16. The method of claim 11 , further comprising:
generating a fourth intermediate signal by buffering and inverting the second intermediate signal based on a second resistance, wherein the second resistance determines, at least in part, a second range of frequencies, and wherein the second resistance provided by a second tunable resistor; and
summing the first intermediate signal with the fourth intermediate signal to generate the equalized signal.

17. The method of claim 16 , wherein the generating of the fourth intermediate signal comprises:
coupling the second intermediate signal to a second cell via the second tunable resistor which includes a second PMOS transistor and a second NMOS transistor.

18. The method of claim 17 , wherein a drain of the second PMOS transistor is coupled to a drain of the second NMOS transistor and a source of the second PMOS transistor is coupled to a source of the second NMOS transistor, the drains of the second PMOS and NMOS transistors being configured to receive the second intermediate signal, and the sources of the second PMOS and NMOS transistors being further coupled to an input of the second cell.

Assignees

• Xilinx Inc

Inventors

• Zheng Kevin
• Chou Chuen-Huei
• Im Hsung Jai

Classifications

• H10D84/0165

  the components including complementary IGFETs, e.g. CMOS devices · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H04L25/03878

  Line equalisers; line build-out devices · CPC title

• H04L25/03019 Primary

  adaptive, i.e. capable of adjustment during data reception · CPC title

• H04L27/01

  Equalisers {(baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005)} · CPC title