Apparatuses and methods for adjusting timing of signals

Patent metadata

Field	Value
Publication number	US-2017264277-A1
Application number	US-201715604297-A
Country	US
Kind code	A1
Filing date	May 24, 2017
Priority date	Dec 3, 2014
Publication date	Sep 14, 2017
Grant date	—

Abstract

Apparatuses and methods for adjusting timing of signals are described herein. An example apparatus may include a first signal adjustment cell configured to receive a first clock signal and to adjust skew of rising or falling edges of the first clock signal based on a first control signal. The timing adjustment circuit may further include a second signal adjustment cell configured to adjust skew of rising or falling edges of a second clock signal based on a second control signal. The timing adjustment circuit may further include a differential adjustment cell configured to receive the first and second clock signals and to adjust skew of rising or falling edges of the first clock signal based on the first control signal and to adjust skew of rising or falling edges of the second clock signal based on the second control signal. The first and second clock signals may be complementary.

First claim

What is claimed is:

1 . An apparatus comprising a clock adjusting circuit, wherein the clock adjusting circuit configured to receive an input clock signal and provide an adjusted clock signal, and wherein the clock adjusting circuit comprises:
an input terminal configured to receive the input clock signal; an output terminal configured to provide the adjusted clock signal; a first bias terminal configured to receive a first bias signal; a first inverter including a first input node and a first output node, the first input node being coupled to the input terminal; and a second inverter including a second input node, a second output node and a first bias node, the second input node being coupled to the first output node of the first inverter, the second output node being coupled to the first input node of the first inverter, the first bias node being couple to the first bias terminal, and the second inverter being configured to serve as a bias-controlled inverter to operate with a drive strength that is based, at least in part, on the first bias signal.

2 . The apparatus of claim 1 , wherein the first inverter is configured to operate with a drive strength that is substantially constant.

3 . The apparatus of claim 2 , wherein the first output node of the first inverter is coupled to the output terminal.

4 . The apparatus of claim 3 , further comprising a duty cycle detection circuit coupled to the output terminal of the clock adjusting circuit, the duty cycle detection circuit being configured to produce the first bias signal responsive, at least in part, to the adjusted clock signal.

5 . The apparatus of claim 4 , wherein the clock adjusting circuit further comprises:
a complementary input terminal configured to receive a complementary input clock signal to the input clock signal; a complementary output terminal configured to provide a complementary adjusted clock signal to the adjusted signal; a second bias terminal configured to receive a second bias signal; a third inverter including a third input node and a third output node, the third input node being coupled to the complementary input terminal, the third output node being coupled to the complementary output terminal, and the third inverter being configured to operate with a drive strength that is substantially constant; and a fourth inverter including a fourth input node, a fourth output node and a second bias node, the fourth input node being coupled to the third output node of the third inverter, the fourth output node being coupled to the third input node of the third inverter, the second bias node being coupled to the second bias terminal, and the fourth inverter being configured to serve as a bias-controlled inverter to operate with a drive strength that is based, at least in part, on the second bias signal; wherein the duty cycle detection circuit is configured to produce the first bias signal and the second bias signal responsive, at least in part, to the adjusted clock signal and the complementary adjusted signal.

6 . The apparatus of claim 5 , wherein the first bias signal and the second bias signal are complementary to each other.

7 . The apparatus of claim 5 , wherein the clock adjusting circuit further comprises:
a fifth inverter including a fifth input node, a fifth output node and a third bias the third bias node being couple to the first bias terminal, and the fifth inverter being configured to serve as a bias-controlled inverter to operate with a drive strength that is based, at least in part, on the first bias signal; and a sixth inverter including a sixth input node, a sixth output node and a fourth bias node, the fourth bias node being couple to the second bias terminal, and the sixth inverter being configured to serve as a bias-controlled inverter to operate with a drive strength that is based, at least in part, on the second bias signal; wherein the fifth and sixth inverters are cross-coupled with each other between the first input terminal and the complementary input terminal.

8 . The apparatus of claim 7 , wherein the first bias signal is complementary to the second bias signal.

9 . The apparatus of claim 7 , wherein the fifth output node of the fifth inverter and the sixth input node of the sixth inverter are coupled to the input terminal, and the fifth input node of the fifth inverter and the sixth output node of the sixth inverter are coupled to the complementary input terminal.

10 . The apparatus of claim 7 , wherein the fifth input node of the fifth inverter and the sixth output node of the sixth inverter are coupled to the input terminal, and the fifth output node of the fifth inverter and the sixth input node of the sixth inverter are coupled to the complementary input terminal.

11 . The apparatus of claim 2 , wherein the adjusting circuit further comprises a third inverter inserted between the input terminal and the first input node of the first inverter, the third inverter including a third input node coupled to the input terminal and a third output node coupled to the output terminal.

12 . The apparatus of claim 11 , further comprising a duty cycle detection circuit coupled to the output terminal of the clock adjusting circuit, the duty cycle detection circuit being configured to produce the first bias signal responsive, at least in part, to the adjusted clock signal.

13 . The apparatus of claim 11 , further comprising an additional clock adjusting circuit coupled to the clock adjusting circuit, wherein the additional adjusting circuit is configured to provide a further adjusted clock signal responsive, at least in part, to the adjusted clock signal and, and wherein the additional clock adjusting circuit comprises:
an additional input terminal configured to receive the adjusted clock signal; an additional output terminal configured to provide the further adjusted clock signal; a second bias terminal configured to receive a second bias signal; a fourth inverter including a fourth input node and a fourth output node, the fourth input node being coupled to the additional input terminal, and the fourth output node being coupled to the additional output terminal; a fifth inverter including a fifth input node and a fifth output node, the fifth input node being coupled to the fourth output node of the fourth invert; and a sixth inverter including a sixth input node, a sixth output node and a second bias node, the sixth input node being coupled to the fifth output node of the fifth inverter, the sixth output node being coupled to the fifth input node of the fifth inverter, the second bias node being couple to the second bias terminal, and the sixth inverter being configured to serve as a bias-controlled inverter to operate with a drive strength that is based, at least in part, on the second bias signal.

14 . The apparatus of claim 13 , wherein the fifth inverter is configured to operate with a drive strength that is substantially constant.

15 . The apparatus of claim 14 , further comprising a duty cycle detection circuit coupled to the additional output terminal of the additional clock adjusting circuit, the duty cycle detection circuit being configured to produce the first bias signal and the second bias signal responsive, at least in part, to the further adjusted clock signal.

16 . The apparatus of claim 15 , wherein each of the first bias signal and second bias signal is an analog signal.

17 . The apparatus of claim 15 , wherein each of the first bias signal and the second bias signal is a digital signal.

18 . The apparatus

Assignees

• Micron Technology Inc

Inventors

• Ma Yantao

Classifications

• H03K5/12 Primary

  by steepening leading or trailing edges · CPC title

• H03K5/05

  by the use of clock signals or other time reference signals · CPC title

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title

• H03K5/134

  with field-effect transistors · CPC title