Semiconductor device including iii-v compound semiconductor layer

Patent metadata

Field	Value
Publication number	US-2025386531-A1
Application number	US-202519303302-A
Country	US
Kind code	A1
Filing date	Aug 18, 2025
Priority date	Apr 27, 2022
Publication date	Dec 18, 2025
Grant date	—

Abstract

A semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a passivation layer, a source doped region, a drain doped region, a source electrode, a drain electrode, a source silicide layer, a drain silicide layer, and a gate electrode. A silicon concentration of a second region of the passivation layer is higher than that of a first region under the second region. The source doped region and the drain doped region are disposed in the III-V compound semiconductor layer. The source electrode and the drain electrode are disposed on the source doped region and the drain doped region, respectively. The source silicide layer is disposed between the source electrode and the source doped region. The drain silicide layer is disposed between the drain electrode and the drain doped region. The source silicide layer and the drain silicide layer are further disposed partly on the passivation layer.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a III-V compound semiconductor layer; a III-V compound barrier layer disposed on the III-V compound semiconductor layer; a passivation layer disposed on the III-V compound barrier layer, wherein the passivation layer comprises:
a first region; and
a second region located above the first region, wherein a silicon concentration of the second region is higher than a silicon concentration of the first region;
a source doped region and a drain doped region disposed in the III-V compound semiconductor layer; a source electrode and a drain electrode disposed on the source doped region and the drain doped region, respectively; a source silicide layer disposed between the source electrode and the source doped region; a drain silicide layer disposed between the drain electrode and the drain doped region, wherein the source silicide layer and the drain silicide layer are further disposed partly on the first region and the second region of the passivation layer; and a gate electrode disposed on the III-V compound semiconductor layer, wherein the source silicide layer and the drain silicide layer are partly disposed on a top surface of the second region.

2 . The semiconductor device according to claim 1 , wherein the source silicide layer and the drain silicide layer are partly disposed on a sidewall of the III-V compound barrier layer, a sidewall of the first region of the passivation layer, and a sidewall of a second region of the passivation layer.

3 . The semiconductor device according to claim 1 , wherein a thickness of the source silicide layer disposed on the second region is greater than a thickness of the source silicide layer disposed on the source doped region, and a thickness of the drain silicide layer disposed on the second region is greater than a thickness of the drain silicide layer disposed on the drain doped region.

4 . The semiconductor device according to claim 1 , wherein the source doped region and the drain doped region are silicon doped regions.

5 . The semiconductor device according to claim 1 , further comprising:
a gate trench penetrating through the passivation layer and the III-V compound barrier layer, wherein at least a part of the gate electrode is disposed in the gate trench.

6 . The semiconductor device according to claim 1 , further comprising:
a recess penetrating through the passivation layer, wherein the gate electrode is located in the recess.

7 . The semiconductor device according to claim 6 , wherein the gate electrode is separated from an inner sidewall of the recess.

8 . The semiconductor device according to claim 6 , wherein the gate electrode comprises a p-type doped III-V compound.

9 . The semiconductor device according to claim 1 , wherein a part of the III-V compound barrier layer is located between the source silicide layer and the source doped region in a vertical direction, and another part of the III-V compound barrier layer is located between the drain silicide layer and the drain doped region in the vertical direction.

10 . The semiconductor device according to claim 1 , wherein an interface between the source silicide layer and the source doped region is lower than an interface between the III-V compound semiconductor layer and the III-V compound barrier layer in a vertical direction, and an interface between the drain silicide layer and the drain doped region is lower than the interface between the III-V compound semiconductor layer and the III-V compound barrier layer in the vertical direction.

Assignees

• United Microelectronics Corp

Inventors

• Lin da-jun
• Chang Chih-Wei
• Tsai Fu-Yu
• Tsai Bin-Siang

Classifications

• H10P30/206

  into Group III-V semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10D64/0116 Primary

  to Group III-V semiconductors · CPC title

• H10D64/411

  for FETs · CPC title