Method for forming a nanowire field effect transistor device having a replacement gate

US9136332B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9136332-B2
Application numberUS-201314101715-A
CountryUS
Kind codeB2
Filing dateDec 10, 2013
Priority dateDec 10, 2013
Publication dateSep 15, 2015
Grant dateSep 15, 2015

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Abstract

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A transistor device and method for forming a field effect transistor device are provided. An example transistor device includes a semiconductor substrate and a device layer. The device layer includes a source region and a drain region that are connected by a channel region that comprises a portion of a nanowire. The channel region is formed by providing a sacrificial layer over the semiconductor substrate. The nanowire is formed over the sacrificial layer, and the sacrificial layer is etched. The etching is selective to the sacrificial layer to prevent the removal of the nanowire, and the etching causes the portion of the nanowire to be suspended over the semiconductor substrate. A gate region is formed that surrounds at least the portion of the nanowire. The gate region is deposited in a conformal manner over all sides of the portion, and the portion is no longer suspended over the semiconductor substrate.

First claim

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It is claimed: 1. A method for forming a nanowire field effect transistor (FET) device, the method comprising: growing a sacrificial layer, a nanowire, and a buffer layer in a fin structure over a semiconductor substrate using an epitaxial process, wherein the buffer layer interposes between the semiconductor substrate and the sacrificial layer; forming a dummy gate around at least a portion of the nanowire, wherein the portion of the nanowire comprises a channel region of a lat…

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What does patent US9136332B2 cover?
A transistor device and method for forming a field effect transistor device are provided. An example transistor device includes a semiconductor substrate and a device layer. The device layer includes a source region and a drain region that are connected by a channel region that comprises a portion of a nanowire. The channel region is formed by providing a sacrificial layer over the semiconducto…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg
What technology area does this patent fall under?
Primary CPC classification B82Y10/00. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Sep 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).