Electronic device

Patent metadata

Field	Value
Publication number	US-2025374429-A1
Application number	US-202418731214-A
Country	US
Kind code	A1
Filing date	May 31, 2024
Priority date	May 31, 2024
Publication date	Dec 4, 2025
Grant date	—

Abstract

An electronic device is provided. The electronic device includes an electronic component and a first group of conductive vias. The electronic component has a first group of terminals disposed on a lower surface of the electronic component and a second group of terminals disposed on an upper surface of the electronic component. The first group of terminals includes a first terminal and a second terminal disposed at different elevations. The first group of conductive vias is electrically connected to the first group of terminals.

First claim

What is claimed is:

1 . An electronic device, comprising:
an electronic component having a first group of terminals disposed on a lower surface of the electronic component and a second group of terminals disposed on an upper surface of the electronic component, wherein the first group of terminals comprise a first terminal and a second terminal disposed at different elevations; and a first group of conductive vias electrically connected to the first group of terminals.

2 . The electronic device of claim 1 , further comprising:
a dielectric structure encapsulating the electronic component and the first group of conductive vias.

3 . The electronic device of claim 2 , wherein the dielectric structure comprises a bottom encapsulant and a top encapsulant stacked over the bottom encapsulant, and the electronic component is embedded within the bottom encapsulant and the top encapsulant.

4 . The electronic device of claim 3 , wherein the bottom encapsulant comprises a protruding portion in contact with the lower surface or a lateral surface extending between the upper surface and the lower surface of the electronic component.

5 . The electronic device of claim 4 , wherein the upper surface of the electronic component has a central region closer to the bottom encapsulant and a peripheral region far away from the bottom encapsulant.

6 . The electronic device of claim 1 , wherein the electronic component comprises a logic die and a carrier disposed between the first group of terminals and the logic die, and the logic die is configured to receive a power through the carrier.

7 . The electronic device of claim 6 , wherein the first group of terminals comprise a first terminal at a central region of the lower surface and a second terminal at a peripheral region of the lower surface, and the first group of conductive vias has a first via connected to the first terminal and a second via connected to the second terminal, and a length of the first via is less than a length of the second via.

8 . The electronic device of claim 6 , further comprising:
a second group of conductive vias connected to the second group of terminals, comprising a first via over a central region of the upper surface and a second via over a peripheral region of the upper surface, and a length of the first via is greater than a length of the second via.

9 . The electronic device of claim 1 , wherein an arrangement of the first group of conductive vias and an arrangement of the second group of conductive vias are non-symmetrical with respect to the electronic component.

10 . An electronic device, comprising:
an electronic component having a lower surface and an upper surface; and a first group of conductive vias disposed under the lower surface of the electronic component and electrically connected to the electronic component, wherein the first group of conductive vias have different lengths.

11 . The electronic device of claim 10 , further comprising:
a first circuit structure supporting the first group of conductive vias, wherein the first group of conductive vias comprise a first via and a second via, a top of the first via is at a first elevation with respect to an upper surface of the first circuit structure, and a top of the second via is at a second elevation, with respect to the upper surface of the first circuit structure, higher than the first elevation.

12 . The electronic device of claim 11 , wherein a bottom of the first via is at a third elevation, and a bottom of the second via is at a fourth elevation substantially the same as the third elevation with respect to the upper surface of the first circuit structure.

13 . The electronic device of claim 10 , further comprising:
a second group of conductive vias disposed over the upper surface of the electronic component and electrically connected to the electronic component, wherein the second group of conductive vias have different lengths.

14 . The electronic device of claim 13 , wherein a sum of a length of one of the first group of conductive vias and a length of one of the second group of conductive vias vertically overlapping the one of the first group of conductive vias is substantially identical to a sum of a length of another one of the first group of conductive vias and a length of another one of the second group of conductive vias directly over the another one of the first group of conductive vias.

15 . The electronic device of claim 13 , further comprising:
a second circuit structure disposed over the second group of conductive vias and connected to the second group of conductive vias, wherein the second group of conductive vias comprise a first via and a second via, a bottom of the first via is at a first elevation with respect to a lower surface of the second circuit structure, and a bottom of the second via is at a second elevation, with respect to the lower surface of the second circuit structure, higher than the first elevation.

16 . The electronic device of claim 15 , wherein the second via is closer to a side, extending between the upper surface and the lower surface, of the electronic component than to the first via.

17 . The electronic device of claim 15 , wherein a top of the first via is at a third elevation, and a top of the second via is at a fourth elevation substantially the same as the third elevation with respect to the lower surface of the second circuit structure.

18 . An electronic device, comprising:
a lower circuit structure having a substantially flat surface; an electronic component disposed over the substantially flat surface of the lower circuit structure, wherein the electronic component has a lower curved surface facing the substantially flat surface; and first interconnections disposed between the substantially flat surface of the lower circuit structure and the lower curved surface of the electronic component.

19 . The electronic device of claim 18 , wherein the electronic component has a first side and a second side opposite to the first side, and a bottom of the first side is at an elevation different from that of a bottom of the second side with respect to the substantially flat surface of the lower circuit structure.

20 . The electronic device of claim 18 , wherein the electronic component has a first side and a second side connected to the first side, and a bottom of the first side is at an elevation different from that of a bottom of the second side with respect to the substantially flat surface of the lower circuit structure.

Assignees

• Advanced Semiconductor Eng

Inventors

• Hsieh Ming-Hao
• Chang Chien-Wei
• Huang Wen Hung
• Huang Min Lung

Classifications

• H05K1/114

  Pad being close to via, but not surrounding the via · CPC title

• H05K3/429

  Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers · CPC title

• H05K2201/10515

  Stacked components · CPC title

• H05K1/162

  incorporating printed capacitors · CPC title

• H05K1/116 Primary

  Lands, clearance holes or other lay-out details concerning the surrounding of a via · CPC title