Barrier structure within a microelectronic enclosure

Patent metadata

Field	Value
Publication number	US-2025368501-A1
Application number	US-202519304827-A
Country	US
Kind code	A1
Filing date	Aug 20, 2025
Priority date	Jan 7, 2021
Publication date	Dec 4, 2025
Grant date	—

Abstract

An example method includes applying a dielectric material on at least a first portion of a first substrate; depositing a seed metal on the dielectric material and on at least a second portion of the first substrate; depositing a plating photoresist on at least a portion of the seed metal; electroplating a metal line on the seed metal within boundaries formed by the plating photoresist; stripping at least a portion of the plating photoresist, and etching at least a portion of the seed metal; and positioning a second substrate relative to a barrier structure formed in part by the metal line to form a cavity.

First claim

What is claimed is:

1 . A method comprising:
applying a dielectric material on at least a first portion of a first substrate; depositing a seed metal on the dielectric material and on at least a second portion of the first substrate; depositing a plating photoresist on at least a portion of the seed metal; electroplating a metal line on the seed metal, wherein the plating photoresist forms a boundary for the metal line, and wherein the metal line forms at least a portion of a barrier structure; stripping at least a portion of the plating photoresist, and etching at least a portion of the seed metal; and positioning a second substrate relative to the barrier structure to form a cavity.

2 . The method of claim 1 , wherein a semiconductor device is disposed inside the cavity.

3 . The method of claim 1 , further comprising:
after etching the at least a portion of the seed metal, removing a portion of the dielectric material.

4 . The method of claim 1 , wherein the second substrate includes one of a silicon wafer and a glass wafer.

5 . The method of claim 1 , wherein the second substrate includes a silicon wafer and a glass wafer.

6 . The method of claim 1 , wherein the positioning of the second substrate comprises:
positioning the second substrate so the second substrate and the barrier structure are separated by a gap of less than 1 micrometer.

7 . The method of claim 1 , wherein the barrier structure has an edge with a slope of 45 degrees or less.

8 . The method of claim 1 , wherein the first substrate includes a semiconductor wafer, a metal layer, and an oxide layer, wherein the applying of the dielectric material on at least a first portion of a first substrate includes applying the dielectric material on at least a first portion of the oxide layer.

9 . The method of claim 1 , wherein a microelectromechanical system (MEMS) device is disposed on the first substrate, the applying of the dielectric material on at least a first portion of the first substrate includes applying the dielectric material on the MEMS device.

10 . A method comprising:
applying a dielectric material on at least a portion of an oxide layer disposed on a first substrate and on a microelectromechanical system (MEMS) device disposed on the oxide layer; depositing a seed metal on the dielectric material and an exposed portion of the oxide layer; depositing a plating photoresist on a first portion of the seed metal; electroplating a metal line on a second portion of the seed metal, wherein the metal line forms at least a portion of a barrier structure; stripping the plating photoresist and a portion of the dielectric material, and etching the first portion of the seed metal to expose the MEMS device; and positioning a second substrate relative to the barrier structure to form a cavity.

11 . The method of claim 10 , further comprising:
before positioning the second substrate, depositing a first metal layer on the second portion of the seed metal.

12 . The method of claim 11 , further comprising:
after depositing the first metal layer and before positioning the second substrate, depositing a second metal layer on the first metal layer.

13 . The method of claim 10 , wherein the applying of the dielectric material includes applying the dielectric material to form a trench defined by the dielectric material and an exposed portion of the oxide layer.

14 . The method of claim 13 , wherein the trench has edges, each of which has a slope of 45 degrees or less.

15 . The method of claim 10 , wherein the seed metal is one or more of titanium, copper, nickel, and gold.

16 . The method of claim 10 , wherein the stripping of the plating photoresist and a portion of the dielectric material and the etching of the first portion of the seed metal form a gap defined in part by the seed metal and the oxide layer.

17 . The method of claim 16 , wherein, after the stripping and the etching, the seed metal and the metal line form a window for the MEMS device.

18 . The method of claim 10 , wherein the MEMS device includes a digital micromirror device.

19 . The method of claim 10 , wherein the second substrate includes at least one of silicon wafer and a glass wafer.

Assignees

• Texas Instruments Inc

Inventors

• Holm Jennifer Lynne
• Jacobs Simon Joshua
• Roby Mary Alyssa Drummond
• Schuck Kathryn Anne
• Taylor Kelly Jay

Classifications

• B81C2203/019

  characterised by the material or arrangement of seals between parts · CPC title

• B81C2203/0136

  Growing or depositing of a covering layer · CPC title

• B81C1/00277 Primary

  for maintaining a controlled atmosphere inside of the cavity containing the MEMS · CPC title

• B81B7/0035

  for maintaining a controlled atmosphere inside of the chamber containing the MEMS · CPC title

• B81B2207/11

  Structural features, others than packages, for protecting a device against environmental influences · CPC title