Device, system and method for providing MEMS structures of a semiconductor package

Patent metadata

Field	Value
Publication number	US-9505610-B2
Application number	US-201314129541-A
Country	US
Kind code	B2
Filing date	Sep 25, 2013
Priority date	Sep 25, 2013
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

Techniques and mechanisms for providing precisely fabricated structures of a semiconductor package. In an embodiment, a build-up carrier of the semiconductor package includes a layer of porous dielectric material. Seed copper and plated copper is disposed on the layer of porous dielectric material. Subsequent etching is performed to remove copper adjacent to the layer of porous dielectric material, forming a gap separating a suspended portion of a MEMS structure from the layer of porous dielectric material. In another embodiment, the semiconductor package includes a copper structure disposed between portions of an insulating layer or portions of a layer of silicon nitride material. The layer of silicon nitride material couples the insulating layer to another insulating layer. One or both of the insulating layers are each protected from desmear processing with a respective release layer structure.

First claim

What is claimed is:

1. A semiconductor package comprising:
a die;
a build-up carrier coupled to the die, the build-up carrier comprising a plurality of build-up layers including a first layer of porous dielectric material; and
a MEMS device having a suspended copper portion anchored by the plurality of build-up layers, wherein a gap separates the suspended copper portion from an exposed surface of the first layer of porous dielectric material, wherein the layer of porous dielectric material has tunnels formed therein, wherein residual copper is disposed within the tunnels.

2. The semiconductor package of claim 1 , wherein the gap separates the suspended copper portion from the exposed surface by a distance equal to or less than three microns.

3. The semiconductor package of claim 2 , wherein a portion of the suspended copper portion above the gap has a thickness of over 30 microns.

4. The semiconductor package of claim 1 , wherein the porous dielectric material comprises an organic resin.

5. The semiconductor package of claim 1 , wherein the build-up carrier comprises a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material couples the MEMS device to a contact point of the die.

6. A method comprising:
forming a first portion of a build-up carrier for a die, including forming a layer of porous dielectric material;
disposing a seed layer on the layer of porous dielectric material;
plating copper on the seed layer; and
after plating the copper, etching copper adjacent to the layer of porous dielectric material to form a suspended portion of a MEMS device, including etching copper to form a gap between the layer of porous dielectric material and the suspended portion of a MEMS device.

7. The method of claim 6 , wherein forming the layer of porous dielectric material includes:
laminating a first dielectric film on a surface;
swelling the first dielectric film; and
after swelling the first dielectric film, performing a desmear etch of the first dielectric film to form a layer of porous dielectric material.

8. The method of claim 6 , wherein the gap separates the suspended copper portion from the exposed surface by a distance equal to or less than three microns.

9. The method of claim 6 , wherein the porous dielectric material comprises an organic resin.

10. The method of claim 6 , wherein the build-up carrier comprises a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to a contact point of the die.

11. A semiconductor package comprising:
a die;
a build-up carrier coupled to the die, the build-up carrier comprising a plurality of build-up layers including:
a first insulating layer and a second insulating layer each including a respective organic dielectric material; and
a layer of silicon nitride material disposed between and adjacent to the first insulating layer and the second insulating layer; and

a copper structure disposed between portions of the second insulating layer or portions of the layer of silicon nitride material, the copper structure coupled via the plurality of build-up layers to a contact point of the die, wherein an air gap separates the copper structure from a surface of the first insulating layer.

12. The semiconductor package of claim 11 , wherein the copper structure includes a suspended portion of a MEMS device.

13. The semiconductor package of claim 11 , wherein the build-up layer comprises an antenna including the copper structure.

14. The semiconductor package of claim 11 , wherein a thickness of the layer of silicon nitride material is less than five hundred nanometers.

15. The semiconductor package of claim 11 , wherein the build-up carrier comprises a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material couples the copper structure to a contact point of the die.

16. A method comprising:
forming a first portion of a build-up carrier for a die, including laminating a first film comprising:
a first insulating layer including an organic dielectric material; and
a first release layer;

after laminating the first film, desmearing a surface of the first portion;
after desmearing the surface of the first portion, separating the first release layer to expose a portion of the first insulating layer;
disposing a first layer of titanium on the exposed portion of the first insulating layer;
forming a first copper structure on the first layer of titanium;
disposing a film of silicon nitride material on the first copper structure; and
laminating a second film on the film of silicon nitride material, the second film comprising:
a second insulating layer including an organic dielectric material; and
a second release layer.

17. The method of claim 16 , further comprising:
after laminating the second film, desmearing another surface of the first portion;
after desmearing the other surface of the first portion, separating the second release layer to expose a portion of the second insulating layer;
disposing a second layer of titanium on the exposed portion of the second insulating layer; and
forming a second copper structure on the second layer of titanium.

18. The method of claim 16 , further comprising:
performing an etch to expose and remove a portion of the silicon nitride material adjoining the first copper structure.

19. The method of claim 18 , wherein the etch removes a portion of the first layer of titanium to form a gap between the first copper structure and the first insulating layer.

Assignees

• Teh Weng Hong
• Ibrahim Tarek A
• Haney Sarah K
• Sobieski Daniel N
• Zantye Parshuram B
• Mair Chad E
• Kamgaing Telesphor
• Intel Corp

Inventors

• Teh Weng Hong
• Ibrahim Tarek A
• Haney Sarah K
• Sobieski Daniel N
• Zantye Parshuram B
• Mair Chad E
• Kamgaing Telesphor

Classifications

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title

• B81C1/00246 Primary

  Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate · CPC title