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Stacked memory chip solution with reduced package inputs/outputs (i/os)
US2025349327A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2025349327-A1 |
| Application number | US-202519213797-A |
| Country | US |
| Kind code | A1 |
| Filing date | May 20, 2025 |
| Priority date | Jul 9, 2021 |
| Publication date | Nov 13, 2025 |
| Grant date | — |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
An apparatus is described. The apparatus includes a logic chip upon which a stack of memory chips is to be placed. The stack of memory chips and the logic chip to be placed within a same package, wherein, multiple memory chips of the stack of memory chips are divided into fractions, and, multiple internal channels within the package that emanate from the logic chip are to be coupled to respective ones of the fractions. The logic chip has a multiplexer. The multiplexer is to multiplex a single input/output (I/O) channel of the package to the multiple internal channels.
First claim
Opening claim text (preview).
1 . An apparatus, comprising: a logic chip upon which a stack of memory chips is to be placed, the stack of memory chips and the logic chip to be placed within a same package, wherein multiple memory chips of the stack of memory chips are divided into fractions, and, multiple internal channels within the package that emanate from the logic chip are to be coupled to respective ones of the fractions, the logic chip comprising a multiplexer, the multiplexer to multiplex a single input/output (I/O) channel of the package to the multiple internal channels.
Assignees
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Classifications
Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title
Optical input buffers · CPC title
Optical output buffers · CPC title
- G11C5/066Primary
Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals · CPC title
Aspects related to pads, pins or terminals · CPC title
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- What does patent US2025349327A1 cover?
- An apparatus is described. The apparatus includes a logic chip upon which a stack of memory chips is to be placed. The stack of memory chips and the logic chip to be placed within a same package, wherein, multiple memory chips of the stack of memory chips are divided into fractions, and, multiple internal channels within the package that emanate from the logic chip are to be coupled to respecti…
- Who is the assignee on this patent?
- Intel Corp
- What technology area does this patent fall under?
- Primary CPC classification G11C5/066. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Thu Nov 13 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).