METHOD OF MANUFACTURING A FinFET BY IMPLANTING A DIELECTRIC WITH A DOPANT

Patent metadata

Field	Value
Publication number	US-2025324653-A1
Application number	US-202519252916-A
Country	US
Kind code	A1
Filing date	Jun 27, 2025
Priority date	Aug 30, 2019
Publication date	Oct 16, 2025
Grant date	—

Abstract

A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

First claim

What is claimed is:

1 . A semiconductor device comprising:
an epitaxial source/drain region over a substrate; a first dielectric layer over the epitaxial source/drain region; a second dielectric layer over the first dielectric layer and over the epitaxial source/drain region, wherein the second dielectric layer comprises an upper region having a higher dopant concentration than a lower region; a contact plug extending through the second dielectric layer and contacting the epitaxial source/drain region, wherein the contact plug is separated from the first dielectric layer and the lower region of the second dielectric layer by an air gap, wherein the upper region of the second dielectric layer extends across the air gap and physically contacts a contact spacer layer adjacent to the contact plug; and a capping layer over the second dielectric layer, a bottom of the capping layer being further away from the substrate than a top of the contact plug.

2 . The semiconductor device of claim 1 , wherein the contact spacer layer has a thickness of between about 2 nm and about 5 nm.

3 . The semiconductor device of claim 2 , wherein the contact spacer layer comprises silicon oxide.

4 . The semiconductor device of claim 2 , wherein the contact spacer layer comprises silicon carbonitride.

5 . The semiconductor device of claim 1 , wherein the contact spacer layer comprises silicon oxynitride.

6 . The semiconductor device of claim 1 , wherein the air gap has a width of between about 0.5 nm and about 4 nm.

7 . The semiconductor device of claim 1 , wherein the contact plug comprises cobalt.

8 . A semiconductor device comprising:
a gate structure adjacent a contact plug over a substrate; a contact spacer layer adjacent to the contact plug; a first dielectric material over the gate structure, wherein the first dielectric material comprises:
a first section comprising a first set of elements; and
a second section comprising the first set of elements and a dopant not present in the first section, the second section in physical contact with the contact spacer layer, the second section extending further away from the substrate than the contact plug;
an air gap extending from the first section to the contact spacer layer; and a capping layer over the first dielectric material.

9 . The semiconductor device of claim 8 , wherein the air gap has a width that varies along a vertical length.

10 . The semiconductor device of claim 9 , wherein a first width of the air gap near a bottom of the air gap is smaller than a second width of the air gap near a top of the air gap.

11 . The semiconductor device of claim 8 , wherein the air gap extends into a source/drain region, the source/drain region underlying the contact plug.

12 . The semiconductor device of claim 8 , wherein the air gap has a bottom surface above a top surface of a source/drain region underlying the contact plug.

13 . The semiconductor device of claim 8 , wherein the capping layer comprises silicon nitride.

14 . The semiconductor device of claim 13 , wherein the capping layer has a thickness of between about 6 nm and about 11 nm.

15 . A semiconductor device comprising:
an air gap laterally surrounding a first portion of a contact plug; an insulating layer laterally surrounding a second portion of the contact plug, the second portion overlying the first portion, wherein a doped portion of the insulating layer overlies the air gap; and a capping layer extending over the insulating layer and the contact plug, wherein an interface between the capping layer and the insulating layer remains above a top surface of the contact plug at all points.

16 . The semiconductor device of claim 15 , wherein the capping layer has a thickness of between about 6 nm and about 16 nm.

17 . The semiconductor device of claim 16 , wherein the capping layer has a thickness of between about 6 nm and about 11 nm.

18 . The semiconductor device of claim 15 , wherein the doped portion comprises xenon.

19 . The semiconductor device of claim 15 , wherein the doped portion comprises argon.

20 . The semiconductor device of claim 15 , wherein the doped portion extends to a depth of less than about 5 nm.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Su-Hao
• Chen Kuo-Ju
• LEE Kai-Hsuan
• Wong I-Hsieh
• Yang Cheng-Yu
• Chen Liang-Yin
• Chang Huicheng
• Yeo Yee-Chia
• Jang Syun-Ming
• Chou Meng-Han

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10P30/40

  into insulating materials · CPC title

• H10P30/22

  using masks · CPC title

• H10W20/0765

  the thin functional dielectric layers being temporary, e.g. sacrificial layers · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title