Semiconductor device structure and methods of forming the same

Patent metadata

Field	Value
Publication number	US-2025318167-A1
Application number	US-202418627507-A
Country	US
Kind code	A1
Filing date	Apr 5, 2024
Priority date	Apr 5, 2024
Publication date	Oct 9, 2025
Grant date	—

Abstract

Methods for forming a semiconductor device structure are described. The method includes forming a fin structure from a substrate, depositing an insulating material around the fin structure, recessing the insulating material, and forming a sacrificial gate structure over a first portion of the fin structure. A first portion of the insulating material is covered by the sacrificial gate structure, and a second portion of the insulating material is exposed. The method further includes modifying a top surface of the exposed second portion of the insulating material, and the modified top surface has a profile different from a top surface of the first portion of the insulating material. After the modifying of the top surface, the method further includes depositing a first spacer on the sacrificial gate structure a second portion of the fin structure and recessing the second portion of the fin structure.

First claim

1 . A method, comprising:
forming a fin structure from a substrate; depositing an insulating material around the fin structure; recessing the insulating material; forming a sacrificial gate structure over a first portion of the fin structure, wherein a first portion of the insulating material is covered by the sacrificial gate structure, and a second portion of the insulating material is exposed; modifying a top surface of the exposed second portion of the insulating material, wherein the modified top surface has a profile different from a top surface of the first portion of the insulating material; after the modifying of the top surface, depositing a first spacer on the sacrificial gate structure and a second portion of the fin structure; and recessing the second portion of the fin structure.

2 . The method of claim 1 , further comprising depositing a second spacer on the first spacer.

3 . The method of claim 2 , further comprising removing horizontal portions of the first and second spacers prior to recessing the second portion of the fin structure.

4 . The method of claim 1 , wherein the second portion of the insulating material is recessed during the recessing of the second portion of the fin structure.

5 . The method of claim 1 , wherein a well portion is exposed after the recessing of the second portion of the fin structure.

6 . The method of claim 5 , further comprising:
depositing a first semiconductor material on the well portion; depositing a second semiconductor material over the first semiconductor material; and depositing a third semiconductor material on the second semiconductor material.

7 . The method of claim 6 , further comprising depositing a dielectric layer on the first semiconductor material, wherein the second semiconductor material is deposited on the dielectric layer.

8 . A method, comprising:
forming a fin structure from a substrate; depositing an insulating material around the fin structure; recessing the insulating material; forming a sacrificial gate structure over a first portion of the fin structure, wherein a first portion of the insulating material is covered by the sacrificial gate structure, and a second portion of the insulating material is exposed; performing a plasma etch process to etch the second portion of the insulating material, wherein a recess is formed in the second portion of the insulating material adjacent the fin structure; depositing a first spacer on the sacrificial gate structure and a second portion of the fin structure, wherein the first spacer is deposited in the recess in the second portion of the insulating material; and recessing the second portion of the fin structure.

9 . The method of claim 8 , wherein the plasma etch process utilizes a main etchant and a secondary etchant.

10 . The method of claim 9 , wherein the main etchant comprises CF 4 , and the secondary etchant comprises Ar.

11 . The method of claim 10 , wherein the plasma etch process comprises pulsing a bias voltage.

12 . The method of claim 8 , wherein the sacrificial gate structure is formed by a wet etch process.

13 . The method of claim 8 , wherein the first portion of the insulating material includes a first top surface having a first center top surface and a first edge top surface.

14 . The method of claim 13 , wherein a first angle formed between the first center top surface and the first edge top surface is an obtuse angle.

15 . The method of claim 14 , wherein the second portion of the insulating material includes a second top surface having a second center top surface and a second edge top surface.

16 . The method of claim 15 , wherein a second angle formed between the second center top surface and the second edge top surface is an acute angle.

17 . A method, comprising:
forming a fin structure from a substrate; depositing an insulating material around the fin structure; recessing the insulating material; forming a sacrificial gate structure over a first portion of the fin structure, wherein a first portion of the insulating material is covered by the sacrificial gate structure, a second portion of the insulating material is exposed, and the first portion of the insulating material includes a first top surface having a first center top surface and a first edge top surface, wherein a highest point of the first edge top surface is at a level substantially higher than a highest point of the first center top surface; modifying a second top surface of the exposed second portion of the insulating material, wherein the second top surface includes a second center top surface and a second edge top surface, and a highest point of the second edge top surface is at a level substantially the same as a highest point of the second center top surface; and depositing a first spacer on the sacrificial gate structure and a second portion of the fin structure.

18 . The method of claim 17 , further comprising depositing a second spacer on the first spacer.

19 . The method of claim 18 , further comprising removing horizontal portions of the first and second spacers and recessing a second portion of the fin structure.

20 . The method of claim 17 . wherein the second top surface is modified by a plasma etch process.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chou Hung-Ju
• Lee Wei-Yang
• Peng Yuan-Ching

Classifications

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D30/014 Primary

  of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors · CPC title

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title