Hyperchip

Patent metadata

Field	Value
Publication number	US-2025300132-A1
Application number	US-202519231070-A
Country	US
Kind code	A1
Filing date	Jun 6, 2025
Priority date	Dec 29, 2016
Publication date	Sep 25, 2025
Grant date	—

Abstract

Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

First claim

What is claimed is:

1 . An integrated circuit assembly, comprising:
a first integrated circuit chip comprising a device side opposite a backside, the device side comprising transistor devices and metal layers, the metal layers comprising a topmost metal layer and a bottommost metal layer, the first integrated circuit chip comprising through silicon vias, the through silicon vias extending from the backside to a location between the bottommost metal layer and the topmost metal layer, and the first integrated circuit chip having a footprint; a second integrated circuit chip coupled to the first integrated circuit chip, the second integrated circuit chip having a device side facing the first integrated circuit chip, the second integrated circuit chip having a plurality of cores, and the second integrated circuit chip having a footprint within the footprint of the first integrated circuit chip; and a heat sink over the second integrated circuit chip, wherein the heat sink extends laterally beyond opposing sides of the second integrated circuit chip.

2 . The integrated circuit assembly of claim 1 , wherein the device side of the first integrated circuit chip is facing toward the device side of the second integrated circuit chip.

3 . The integrated circuit assembly of claim 1 , wherein the heat sink extends laterally beyond opposing sides of the first integrated circuit chip.

4 . The integrated circuit assembly of claim 1 , wherein the second integrated circuit chip is electrically coupled to the through silicon vias of the first integrated circuit chip.

5 . The integrated circuit assembly of claim 1 , further comprising:
a third integrated circuit chip coupled to the first integrated circuit chip, the third integrated circuit chip laterally spaced apart from the second integrated circuit chip.

6 . The integrated circuit assembly of claim 1 , further comprising:
a package substrate, wherein the first integrated circuit chip is coupled to the package substrate.

7 . The integrated circuit assembly of claim 1 , wherein the second integrated circuit chip is coupled to the first integrated circuit chip by bump-to-bump bonding.

8 . An integrated circuit assembly, comprising:
a first die comprising a first side opposite a second side, the first side comprising transistor devices and metal layers, the metal layers comprising a first metal layer proximate to the transistor devices and a last metal layer distal from the transistor devices, the first die comprising through silicon vias, the through silicon vias extending from the second side to a location between the last metal layer and the first metal layer, and the first die having a lateral width; a second die coupled to the first die, the second die having a first side facing toward the first die, the second die having a plurality of cores, and the second die having a lateral width within the lateral width of the first die; and a heat sink over the second die, wherein the heat sink extends laterally beyond the lateral width of the second die.

9 . The integrated circuit assembly of claim 8 , wherein the first side of the first die is between the first side of the second die and the second side of the first die.

10 . The integrated circuit assembly of claim 8 , wherein the heat sink extends laterally beyond the lateral width of the first die.

11 . The integrated circuit assembly of claim 8 , wherein the second die is electrically coupled to the through silicon vias of the first die.

12 . The integrated circuit assembly of claim 8 , further comprising:
a third die coupled to the first die, the third die laterally spaced apart from the second die.

13 . The integrated circuit assembly of claim 8 , further comprising:
a package substrate, wherein the first die is coupled to the package substrate.

14 . A method of fabricating an integrated circuit assembly, the method comprising:
providing a first integrated circuit chip comprising a device side opposite a backside, the device side comprising transistor devices and metal layers, the metal layers comprising a topmost metal layer and a bottommost metal layer, the first integrated circuit chip comprising through silicon vias, the through silicon vias extending from the backside to a location between the bottommost metal layer and the topmost metal layer, and the first integrated circuit chip having a footprint; coupling a second integrated circuit chip to the first integrated circuit chip, the second integrated circuit chip having a device side facing the first integrated circuit chip, the second integrated circuit chip having a plurality of cores, and the second integrated circuit chip having a footprint within the footprint of the first integrated circuit chip; and providing a heat sink over the second integrated circuit chip, wherein the heat sink extends laterally beyond opposing sides of the second integrated circuit chip.

15 . The method of claim 14 , wherein the device side of the first integrated circuit chip is facing toward the device side of the second integrated circuit chip.

16 . The method of claim 14 , wherein the heat sink extends laterally beyond opposing sides of the first integrated circuit chip.

17 . The method of claim 14 , wherein the second integrated circuit chip is electrically coupled to the through silicon vias of the first integrated circuit chip.

18 . The method of claim 14 , further comprising:
coupling a third integrated circuit chip to the first integrated circuit chip, the third integrated circuit chip laterally spaced apart from the second integrated circuit chip.

19 . The method of claim 14 , further comprising:
coupling a package substrate to the first integrated circuit chip.

20 . The method of claim 14 , wherein coupling the second integrated circuit chip to the first integrated circuit chip comprises using bump-to-bump bonding.

Assignees

• Intel Corp

Inventors

• Bohr Mark T
• Gomes Wilfred
• Kumar Rajesh
• Tadayon Pooya
• Ingerly Doug

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title