Semiconductor device and methods for forming the same

Patent metadata

Field	Value
Publication number	US-2025294797-A1
Application number	US-202418739888-A
Country	US
Kind code	A1
Filing date	Jun 11, 2024
Priority date	Mar 15, 2024
Publication date	Sep 18, 2025
Grant date	—

Abstract

A semiconductor device includes a substrate, a first well region of the first conductivity type, and a second well region of the second conductivity type. The semiconductor device also includes a drain region, a source region, and a gate structure. The drain region of the first conductivity type is formed in the first well region and the source region of the first conductivity type is formed in the second well region. The gate structure on the substrate includes the first gate stack near the source region and the second gate stack near the drain region. The first gate stack includes the first gate dielectric layer and the first gate electrode layer. The second gate stack includes the second gate dielectric layer and the second gate electrode layer. The thickness of the first gate dielectric layer is different from the thickness of the second gate dielectric layer.

First claim

What is claimed is:

1 . A semiconductor device, including:
a substrate; a first well region in the substrate, wherein the first well region has a first conductivity type; a second well region in the substrate and adjacent to the first well region, wherein the second well region has a second conductivity type; a drain region in the first well region, wherein the drain region extends downward from a top surface of the first well region into the first well region, and the drain region has the first conductivity type; a source region in the second well region, wherein the source region extends downward from a top surface of the second well region into the second well region, and the source region has the first conductivity type; and a gate structure formed on the substrate and positioned between the source region and the drain region, wherein the gate structure comprises: a first gate stack near the source region, wherein the first gate stack includes a first gate dielectric layer on the substrate and a first gate electrode layer on the first gate dielectric layer; and a second gate stack near the drain region, wherein the second gate stack includes a second gate dielectric layer on the substrate and a second gate electrode layer on the second gate dielectric layer, wherein a thickness of the first gate dielectric layer is different from a thickness of the second gate dielectric layer.

2 . The semiconductor device as claimed in claim 1 , wherein the thickness of the first gate dielectric layer is greater than the thickness of the second gate dielectric layer.

3 . The semiconductor device as claimed in claim 1 , wherein a thickness of the first gate electrode layer is different from a thickness of the second gate electrode layer.

4 . The semiconductor device as claimed in claim 1 , wherein a thickness of the first gate electrode layer is greater than a thickness of the second gate electrode layer.

5 . The semiconductor device as claimed in claim 1 , wherein the first gate electrode layer and the second gate electrode layer are laterally separated from each other by a gap, and the gap is correspondingly positioned above the first well region.

6 . The semiconductor device as claimed in claim 1 , wherein the first gate stack and the second gate stack are two electrically independent gate stacks.

7 . The semiconductor device as claimed in claim 1 , further including:
an insulating cap layer on the second gate stack, wherein the insulating cap layer covers the second gate electrode layer; a spacer on sidewalls of the second gate electrode layer and sidewalls of the insulating cap layer.

8 . The semiconductor device as claimed in claim 7 , wherein the second gate electrode layer is electrically isolated from the first gate electrode layer by the spacer.

9 . The semiconductor device as claimed in claim 7 , wherein an extension portion of the first gate electrode layer is disposed above the spacer and covers the spacer.

10 . The semiconductor device as claimed in claim 7 , wherein an extension portion of the first gate electrode layer is disposed above the spacer and the insulating cap layer, and the extension portion covers the spacer and a portion of the insulating cap layer.

11 . The semiconductor device as claimed in claim 7 , wherein a thickness of the insulating cap layer is greater than a bottom width of the spacer.

12 . The semiconductor device as claimed in claim 1 , wherein there is a first distance between a bottom surface of the first gate electrode layer and a bottom surface of the second gate electrode layer, and an extension portion of the first gate electrode layer is higher than a top surface of the second gate electrode layer, wherein there is a second distance between a bottom surface of the extension portion and a top surface of a main portion of the second gate electrode layer, and the first distance is less than the second distance.

13 . The semiconductor device as claimed in claim 1 , wherein an extension portion of the first gate electrode layer is disposed above the second gate electrode layer, and the extension portion and the second gate electrode layer form an overlapping area.

14 . The semiconductor device as claimed in claim 1 , further comprising:
an insulating layer on the first well region, wherein the second gate electrode layer is disposed across the insulating layer, wherein the second gate dielectric layer is adjacent to the insulating layer, and a thickness of the insulating layer is greater than a thickness of the second gate dielectric layer.

15 . The semiconductor device as claimed in claim 1 , wherein the thickness of the first gate dielectric layer and the thickness of the second gate dielectric layer differ by at least 20 angstrom or more.

16 . A method for forming a semiconductor device, including:
providing a substrate; forming a first well region and a second well region in the substrate, wherein the first well region has a first conductivity type and the second well region has a second conductivity type; forming a drain region in the first well region and a source region in the second well region, wherein the drain region and the source region have the first conductivity type; forming a gate structure over the substrate, wherein the gate structure is disposed between the source region and the drain region, and the gate structure comprises:
a first gate stack near the source region, wherein the first gate stack includes a first gate dielectric layer on the substrate and a first gate electrode layer on the first gate dielectric layer; and
a second gate stack near the drain region, wherein the second gate stack includes a second gate dielectric layer on the substrate and a second gate electrode layer on the second gate dielectric layer,
wherein a thickness of the first gate dielectric layer is different from a thickness of the second gate dielectric layer.

17 . The method for forming a semiconductor device as claimed in claim 16 , wherein the thickness of the first gate dielectric layer is greater than the thickness of the second gate dielectric layer.

18 . The method for forming a semiconductor device as claimed in claim 16 , wherein a thickness of the first gate electrode layer is different from a thickness of the second gate electrode layer.

19 . The method for forming a semiconductor device as claimed in claim 16 , wherein a thickness of the first gate electrode layer is greater than a thickness of the second gate electrode layer.

20 . The method for forming a semiconductor device as claimed in claim 16 , wherein the first gate electrode layer and the second gate electrode layer are laterally separated from each other by a gap, and the gap is correspondingly positioned above the first well region.

21 . The method for forming a semiconductor device as claimed in claim 16 , wherein the first gate stack and the second gate stack are two electrically independent gate stacks.

22 . The method for forming a semiconductor device as claimed in claim 16 , further comprising:
forming an insulating cap layer on the second gate stack, wherein the insulating cap layer covers a top surface of the second gate electrode layer; and forming a spacer on sidewalls of the second gate electrode layer and sidewalls of the insulating cap layer, wherein the second gate electrode layer and the first gate electrode layer are electrically isolated from each other by the spacer.

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Assignees

• Vanguard Int Semiconduct Corp

Inventors

• Liao Hsueh-Chun
• Lin Po-Heng
• Lee Chia-Hao
• Chang Che-Hua
• Lao Chung-Ren
• Liao Chih-Cherng
• Liu Chwen-Ming

Classifications

• H10D64/111

  Field plates · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title

• H10D30/65

  Lateral DMOS [LDMOS] FETs · CPC title

• H10D30/611 Primary

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title