Embedded cooling systems for advanced device packaging

Patent metadata

Field	Value
Publication number	US-2025273538-A1
Application number	US-202519058623-A
Country	US
Kind code	A1
Filing date	Feb 20, 2025
Priority date	Dec 23, 2022
Publication date	Aug 28, 2025
Grant date	—

Abstract

In some implementations, a device package may include a package substrate, a package cover disposed on the package substrate, and an integrated cooling assembly disposed between the package substrate and the package cover. The integrated cooling assembly may include a semiconductor device and a cold plate having a first side attached to the semiconductor device and a second side opposite the first side. An adhesive layer may be disposed between the package cover and the second side of the cold plate, and one or more surfaces of second side of the cold plate may be spaced apart from the package cover to define a coolant channel therebetween. The adhesive layer may seal the package cover to the cold plate around a perimeter of the coolant channel.

First claim

1 . (canceled)

2 . A device package comprising:
a package substrate; a package cover disposed on the package substrate; an integrated cooling assembly disposed between the package substrate and the package cover, the integrated cooling assembly comprising a first semiconductor device, one or more second semiconductor devices arranged in a device stack, and a cold plate, wherein:
the cold plate comprises a first side and a second side opposite the first side; and
the first semiconductor device and the device stack are each attached to the first side of the cold plate; and
an adhesive layer disposed between the package cover and the second side of the cold plate, wherein:
one or more surfaces of the second side of the cold plate are spaced apart from the package cover to define a coolant channel therebetween; and
the adhesive layer seals the package cover to the cold plate around a perimeter of the coolant channel.

3 . The device package of claim 2 , wherein the first semiconductor device and the device stack are each attached to the first side of the cold plate in a side-by-side arrangement.

4 . The device package of claim 2 , the cold plate is attached to the first semiconductor device and the device stack by direct dielectric bonds.

5 . The device package of claim 2 , wherein the cold plate is attached to the first semiconductor device and the device stack by direct hybrid bonds.

6 . The device package of claim 2 , further comprising a coolant fluid disposed in the coolant channel.

7 . The device package of claim 2 , wherein the coolant channel forms a fluid pathway between an inlet and outlet openings disposed through the package cover.

8 . The device package of claim 2 , further comprising an underfill layer that at least partially encapsulates the integrated cooling assembly in regions outside of the coolant channel.

9 . The device package of claim 2 , wherein:
the second side of the cold plate comprises a base surface and sidewalls that surround the base surface and extend upwardly therefrom to form a cavity; and a first portion of the adhesive layer is disposed between the sidewalls and the package cover.

10 . The device package of claim 9 , wherein the adhesive layer comprises one or more second portions attaching the cold plate and the package cover in one or more locations inward of the perimeter of the coolant channel.

11 . The device package of claim 9 , wherein the second side of the cold plate further comprises a plurality of protruding features that extend upwardly from the base surface.

12 . The device package of claim 11 , wherein the protruding features comprise a thermally conductive metal.

13 . The device package of claim 2 , wherein the integrated cooling assembly further comprises a thermoelectric cooler disposed between a hotspot region of the first semiconductor device or the device stack and portion of the cold plate disposed over the hotspot region.

14 . The device package of claim 13 , wherein the thermoelectric cooler is electrically coupled to the package substrate through interconnects disposed through the first semiconductor device or the device stack.

15 . The device package of claim 13 , wherein:
the second side of the cold plate comprises a plurality of protruding features; and a pattern density, size, and/or shape of the protruding features in a region above the thermoelectric cooler is different from adjacent regions.

16 . The device package of claim 13 , wherein the thermoelectric cooler is directly bonded to at least one of the cold plate, the first semiconductor device, or the device stack.

17 . The device package of claim 2 , wherein:
the adhesive layer comprises a first portion that seals the seals the package cover to the cold plate around the perimeter of the coolant channel and a second portion disposed inward of the perimeter of the coolant channel; and the second portion of the adhesive layer attaches inner surfaces of the cold plate to the corresponding portions of the package cover disposed thereover.

18 . The device package of claim 9 , wherein an inward facing surface of the package cover comprises a continuous well-region sized and shaped to receive a portion of the sidewalls of the cold plate.

19 . The device package of claim 18 , wherein the adhesive layer comprises a compliant material that surrounds an upper portion of the sidewalls disposed in the well-region.

20 . The device package of claim 19 , wherein:
the cold plate further comprises one or more inner supports that connect an opposing pair of the sidewalls; and the continuous well-region is sized and shaped to receive upper portions of the inner supports.

21 . The device package of claim 20 , wherein the adhesive layer at least partially surrounds an upper portion of the inner supports disposed in the well-region.

22 . The device package of claim 20 , wherein:
the cold plate comprises a first plate and a second plate directly bonded to the first plate; and the second plate forms the upper portions of the sidewalls at least partially disposed in the well-region.

Assignees

• Adeia Semiconductor Bonding Technologies Inc

Inventors

• Gao Guilian
• Haba Belgacem
• Mirkarimi Laura

Classifications

• H10W90/796

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W76/15

  Containers comprising an insulating or insulated base · CPC title

• H10W40/28

  comprising Peltier coolers · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title