Integrated circuit structure with backside dielectric layer having air gap

Patent metadata

Field	Value
Publication number	US-2025266293-A1
Application number	US-202519185471-A
Country	US
Kind code	A1
Filing date	Apr 22, 2025
Priority date	Apr 29, 2020
Publication date	Aug 21, 2025
Grant date	—

Abstract

An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is on a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is on a backside of the source epitaxial structure and a backside of the drain epitaxial structure and has an air gap therein. The backside via extends through the backside dielectric layer to a first one of the source epitaxial structure and the drain epitaxial structure.

First claim

What is claimed is:

1 . A method of forming a semiconductor device, the method comprising:
forming a channel structure over a substrate; forming a first recess in the substrate adjacent the channel structure; forming a plug in the first recess; forming an epitaxial structure over the plug, the epitaxial structure extending along sidewalls of the channel structure; forming a first gate structure over the channel structure; forming a front-side interconnection structure on a front-side of the substrate; removing at least a portion of the substrate to expose the plug; forming a cap layer over the plug; forming a dielectric layer along sidewalls of the plug and the cap layer, wherein the dielectric layer encloses a void; removing at least a portion of the cap layer and the plug to form a second recess in the dielectric layer; and forming a first backside via in the second recess, wherein the first backside via is electrically connected to the epitaxial structure.

2 . The method of claim 1 , wherein forming the channel structure comprises forming a stack of channel layers.

3 . The method of claim 1 , wherein a width of the cap layer is greater than a width of the plug.

4 . The method of claim 1 , wherein the dielectric layer completely surrounds the void.

5 . The method of claim 1 , wherein the void is closer to the channel structure than the cap layer.

6 . The method of claim 1 , wherein the cap layer extends further from the channel structure than the void.

7 . The method of claim 1 , wherein the plug extends further from the channel structure than the void.

8 . A method of forming a semiconductor device, the method comprising:
forming a first channel structure and a second channel structure over a substrate forming a first recess in the substrate adjacent the first channel structure; forming a second recess in the substrate adjacent the second channel structure forming a first plug in the first recess and a second plug in the second recess; forming a first epitaxial structure over the first plug, the first epitaxial structure extending along sidewalls of the first channel structure; forming a second epitaxial structure over the second plug, the second epitaxial structure extending along sidewalls of the second channel structure; removing at least a portion of the substrate to expose the first plug and the second plug; forming a dielectric layer between the first plug and the second plug, wherein the dielectric layer includes a void between the first plug and the second plug; replacing at least a portion of the first plug with a first via; and replacing at least a portion of the second plug with a second via.

9 . The method of claim 8 , further comprising:
prior to forming the dielectric layer, forming a first cap layer over the first plug and forming a second cap layer over the second plug.

10 . The method of claim 9 , wherein the first cap layer and the second cap layer are faceted.

11 . The method of claim 9 , wherein removing at least a portion of the substrate comprises removing a first portion of the substrate, further comprising:
after forming the first cap layer and the second cap layer and prior to forming the dielectric layer, removing a second portion of the substrate.

12 . The method of claim 8 , wherein the void has a tapered profile with a width decreasing as the void extends through the dielectric layer away from the first epitaxial structure and the second epitaxial structure.

13 . The method of claim 8 , wherein forming the first via comprises forming a silicide layer on the first epitaxial structure.

14 . The method of claim 8 , further comprising forming a gate structure over the first channel structure, wherein the dielectric layer physically contacts the gate structure.

15 . A method of forming a semiconductor device, the method comprising:
etching a recess in a substrate; forming a sacrificial plug in the recess in the substrate; forming a first source/drain epitaxial structure over the sacrificial plug; forming a second source/drain epitaxial structure over the substrate; forming a gate structure laterally between the first source/drain epitaxial structure and the second source/drain epitaxial structure; removing at least a portion of the substrate adjacent the sacrificial plug; forming a dielectric layer adjacent the sacrificial plug, the dielectric layer having a void therein; and replacing the sacrificial plug with a conductive via.

16 . The method of claim 15 , wherein removing at least a portion of the substrate comprises removing a first portion and removing a second portion, further comprising:
after removing the first portion and before removing the second portion, forming a cap layer over the sacrificial plug, wherein removing the second portion is performed after forming the cap layer.

17 . The method of claim 16 , wherein the void extends closer to the gate structure than the cap layer.

18 . The method of claim 17 , wherein a width of the void narrows as the void extends toward a first surface of the dielectric layer, wherein the first surface of the dielectric layer faces away from the first source/drain epitaxial structure and the second source/drain epitaxial structure.

19 . The method of claim 15 , wherein a width of the conductive via decreases and then increases as the conductive via extends away from the first source/drain epitaxial structure.

20 . The method of claim 15 , wherein the void is laterally aligned with a third source/drain epitaxial structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Che-Lun
• Lee Wei-Yang
• Lin Chia-Pin
• Peng Yuan-Ching

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title