Interconnect Structure of Semiconductor Device

Patent metadata

Field	Value
Publication number	US-2025259889-A1
Application number	US-202519190940-A
Country	US
Kind code	A1
Filing date	Apr 28, 2025
Priority date	Sep 11, 2020
Publication date	Aug 14, 2025
Grant date	—

Abstract

A method includes forming a first conductive feature in a first dielectric layer. A second dielectric layer is formed over the first conductive feature and the first dielectric layer. An opening is formed in the second dielectric layer. The opening exposes a top surface of the first conductive feature. The top surface of the first conductive feature includes a first metallic material and a second metallic material different from the first metallic material. A native oxide layer is removed from the top surface of the first conductive feature. A surfactant soaking process is performed on the top surface of the first conductive feature. The surfactant soaking process forms a surfactant layer over the top surface of the first conductive feature. A first barrier layer is deposited on a sidewall of the opening. The surfactant layer remains exposed at the end of depositing the first barrier layer.

First claim

What is claimed is:

1 . A method comprising:
forming a first conductive feature in a first dielectric layer; forming a second dielectric layer over the first conductive feature and the first dielectric layer; forming an opening in the second dielectric layer, the opening exposing a top surface of the first conductive feature; performing a surfactant soaking process on the top surface of the first conductive feature, the surfactant soaking process forming a surfactant layer over the top surface of the first conductive feature; depositing a first barrier layer on a sidewall of the opening, wherein the surfactant layer remains exposed after depositing the first barrier layer; depositing a first adhesion layer over the first barrier layer; after forming the first adhesion layer, removing the surfactant layer; and forming a second conductive feature in the opening over the first adhesion layer.

2 . The method of claim 1 , wherein the second conductive feature contacts the second dielectric layer.

3 . The method of claim 1 , further comprising:
prior to forming the second dielectric layer, forming a capping layer over the top surface of the first conductive feature.

4 . The method of claim 3 , wherein the second conductive feature contacts the capping layer.

5 . The method of claim 1 , wherein the second conductive feature comprises a seed layer and a conductive fill over the seed layer.

6 . The method of claim 1 , wherein the first barrier layer contacts the second conductive feature.

7 . The method of claim 1 , wherein the first adhesion layer contacts the first conductive feature.

8 . A method comprising:
forming a first conductive feature in a first dielectric layer; forming a second dielectric layer over the first conductive feature and the first dielectric layer; forming an opening in the second dielectric layer, the opening exposing a top surface of the first conductive feature; performing a surfactant soaking process on the top surface of the first conductive feature, the surfactant soaking process forming a surfactant layer over the top surface of the first conductive feature; depositing a first barrier layer on a sidewall of the opening, wherein the surfactant layer remains exposed after depositing the first barrier layer; after forming the first barrier layer, removing the surfactant layer; and after removing the surfactant layer, depositing a first adhesion layer over the first barrier layer; and forming a second conductive feature in the opening over the first adhesion layer.

9 . The method of claim 8 , further comprising:
after removing the surfactant layer and prior to depositing the first adhesion layer, forming a second barrier layer, wherein the first adhesion layer is formed over the second barrier layer.

10 . The method of claim 9 , wherein the first barrier layer and the second barrier layer comprise a same material.

11 . The method of claim 9 , wherein the second barrier layer contacts the second dielectric layer.

12 . The method of claim 9 , further comprising:
prior to forming the second dielectric layer, forming a capping layer over the top surface of the first conductive feature.

13 . The method of claim 12 , wherein the second barrier layer contacts the capping layer.

14 . The method of claim 8 , wherein a corner of the second conductive feature has a concave surface.

15 . A method comprising:
forming a first conductive feature in a first dielectric layer; forming a second dielectric layer over the first conductive feature and the first dielectric layer; forming an opening in the second dielectric layer, the opening exposing a top surface of the first conductive feature; performing a surfactant soaking process on the top surface of the first conductive feature, the surfactant soaking process forming a surfactant layer over the top surface of the first conductive feature; depositing a first barrier layer on a sidewall of the opening, wherein the surfactant layer remains exposed after depositing the first barrier layer; after forming the first barrier layer, forming a second barrier layer over the first barrier layer and along a bottom of the opening; after forming the second barrier layer, depositing a first adhesion layer over the second barrier layer; and forming a second conductive feature in the opening over the first adhesion layer.

16 . The method of claim 15 , further comprising:
prior to depositing the second barrier layer, removing the surfactant layer.

17 . The method of claim 15 , further comprising:
prior to forming the second dielectric layer, forming a capping layer over the top surface of the first conductive feature.

18 . The method of claim 17 , wherein the second barrier layer contacts the capping layer.

19 . The method of claim 15 , wherein a corner of the second conductive feature has a concave surface.

20 . The method of claim 15 , wherein the second barrier layer is spaced apart from the second dielectric layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Yao-Min
• Kuo Chia-Pang
• Chin Shu-Cheng
• Chi Chih-Chien
• Weng Cheng-Hui
• Su Hung-Wen
• Tsai Ming-Hsing

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/0765

  the thin functional dielectric layers being temporary, e.g. sacrificial layers · CPC title

• H10W20/037

  the barrier, adhesion or liner layers being on top of a main fill metal · CPC title