Structures including a photodetector and multiple deep trenches

Patent metadata

Field	Value
Publication number	US-2025255023-A1
Application number	US-202418432229-A
Country	US
Kind code	A1
Filing date	Feb 5, 2024
Priority date	Feb 5, 2024
Publication date	Aug 7, 2025
Grant date	—

Abstract

Structures including a photodetector, such as a single-photon avalanche diode, and related methods. The structure comprises a semiconductor layer, a photodetector including a well in the semiconductor layer, and a deep trench isolation region including a first conductor layer extending through the semiconductor layer. The deep trench isolation region surrounds the photodetector. The structure further comprises a bond pad, and an electrical connection including a second conductor layer extending from the bond pad through the semiconductor layer.

First claim

What is claimed is:

1 . A structure comprising:
a semiconductor layer; a photodetector including a well in the semiconductor layer; a deep trench isolation region including a first conductor layer extending through the semiconductor layer, the deep trench isolation region surrounding the photodetector; a bond pad; and an electrical connection including a second conductor layer extending from the bond pad through the semiconductor layer.

2 . The structure of claim 1 wherein the first conductor layer and the second conductor layer comprise tungsten.

3 . The structure of claim 1 wherein the photodetector is a single-photon avalanche detector.

4 . The structure of claim 1 wherein the first conductor layer has a first top surface, and the second conductor layer has a second top surface that is coplanar with the first top surface.

5 . The structure of claim 4 wherein the first conductor layer has a first bottom surface opposite from the first top surface, the second conductor layer has a second bottom surface opposite from the second top surface, and the second bottom surface is coplanar with the first bottom surface.

6 . The structure of claim 5 wherein the first conductor layer has a first height between the first top surface and the first bottom surface, the second conductor layer has a second height between the second top surface and the second bottom surface, and the second height is equal to the first height.

7 . The structure of claim 1 wherein the first conductor layer has a first bottom surface, the second conductor layer has a second bottom surface, and the second bottom surface is coplanar with the first bottom surface.

8 . The structure of claim 7 further comprising:
a back-end-of-line stack on the semiconductor layer, the back-end-of-line stack including a plurality of interlayer dielectric layers and a first metal feature in the plurality of interlayer dielectric layers,
wherein the first bottom surface of the first conductor layer is coextensive with the first metal feature.

9 . The structure of claim 8 wherein the back-end-of-line stack includes a second metal feature in the plurality of interlayer dielectric layers, and the second bottom surface of the second conductor layer is coextensive with the second metal feature.

10 . The structure of claim 9 wherein the first metal feature and the second metal feature are disposed in the same metallization level of the back-end-of-line stack.

11 . The structure of claim 9 wherein the first conductor layer has a first height and the second conductor layer a second height that is equal to the first height.

12 . The structure of claim 8 wherein the first metal feature is electrically floating.

13 . The structure of claim 1 further comprising:
a back-end-of-line stack on the semiconductor layer, the back-end-of-line stack including a plurality of interlayer dielectric layers and a first metal feature in the plurality of interlayer dielectric layers,
wherein the first conductor layer extends into the plurality of interlayer dielectric layers of the back-end-of-line stack, and the first conductor layer is coextensive with the first metal feature.

14 . The structure of claim 13 wherein the back-end-of-line stack includes a second metal feature in the plurality of interlayer dielectric layers, the second conductor layer extends into the plurality of interlayer dielectric layers of the back-end-of-line stack, and the second conductor layer is coextensive with the second metal feature.

15 . The structure of claim 1 wherein the deep trench isolation region includes a first dielectric layer disposed between the first conductor layer and the semiconductor layer, and the electrical connection includes a second dielectric layer disposed between the second conductor layer and the semiconductor layer.

16 . The structure of claim 15 wherein the first dielectric layer has a first thickness, and the second dielectric layer has a second thickness that is equal to the first thickness.

17 . The structure of claim 1 wherein the electrical connection includes a first plurality of trenches having a first pitch, the deep trench isolation region includes a second plurality of trenches having a second pitch, and the second pitch is greater than the first pitch.

18 . The structure of claim 1 wherein the bond pad comprises a first metal, and the second conductor layer comprises a second metal different from the first metal.

19 . A method comprising:
forming a photodetector including a well in a semiconductor layer; forming a deep trench isolation region including a first conductor layer extending through the semiconductor layer, wherein the deep trench isolation region surrounds the photodetector; and forming an electrical connection including a second conductor layer extending from a bond pad through the semiconductor layer.

20 . The method of claim 19 wherein the first conductor layer and the second conductor layer are concurrently planarized by chemical-mechanical polishing.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Yi Wanbing
• Ng Yong Chau
• Li Xiaodong
• Qiu Weichu

Classifications

• H10F39/811

  Interconnections · CPC title

• H10F39/011

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• H10F39/18

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title

• H10F39/807 Primary

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