Tsv as pad

Patent metadata

Field	Value
Publication number	US-2025253294-A1
Application number	US-202419003994-A
Country	US
Kind code	A1
Filing date	Dec 27, 2024
Priority date	Jun 13, 2018
Publication date	Aug 7, 2025
Grant date	—

Abstract

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a through-silicon via (TSV) may be disposed through at least one of the microelectronic substrates. The TSV is exposed at the bonding interface of the substrate and functions as a contact surface for direct bonding.

First claim

1 . (canceled)

2 . A microelectronic structure having a back side, the microelectronic structure comprising:
a semiconductor base substrate; an electrically conductive via partly or fully through the semiconductor base substrate and exposed at the back side of the microelectronic structure; a dielectric layer having a first portion extending over the semiconductor base substrate and a second portion extending from the first portion along a portion of the electrically conductive via; an insulating layer over the first portion of the dielectric layer, wherein the second portion of the dielectric layer is between the insulating layer and the portion of the electrically conductive via; and a bonding surface at the back side of the microelectronic structure at least partially defined by an exposed end portion of the electrically conductive via, and a nonconductive bonding layer including a surface of the insulating layer.

3 . The microelectronic structure of claim 2 , wherein the bonding surface is a direct bonding surface.

4 . The microelectronic structure of claim 3 , wherein the insulating layer is activated at the bonding surface.

5 . The microelectronic structure of claim 2 , wherein the dielectric layer comprises a diffusion barrier.

6 . The microelectronic structure of claim 2 , wherein the nonconductive bonding layer further comprises a surface of the second portion of the dielectric layer.

7 . A bonded structure comprising:
the microelectronic structure of claim 2 ; and a second substrate having a front side and a back side, the front side including a nonconductive bonding layer and an exposed pad, wherein the nonconductive bonding layer of the front side of the second substrate is bonded to the nonconductive bonding layer of the back side of the first substrate, and wherein the exposed pad of the second substrate is bonded to the exposed end portion of the electrically conductive via.

8 . The bonded structure of claim 7 , wherein the second substrate is hybrid bonded to the microelectronic structure, without an intervening adhesive.

9 . The bonded structure of claim 7 wherein the exposed pad is embedded at least partially in the second substrate.

10 . The bonded structure of claim 7 , further comprising a second electrically conductive via partly or fully through a semiconductor material of the second substrate.

11 . The bonded structure of claim 10 , wherein the second electrically conductive via is in electrical communication with the exposed pad.

12 . The bonded structure of claim 11 , wherein the second electrically conductive via of the second substrate is in electrical communication with the electrically conductive via of the microelectronic structure.

13 . A microelectronic structure having a back side, the microelectronic structure comprising:
a semiconductor base substrate; an electrically conductive via partly or fully through the semiconductor base substrate and exposed at the back side of the microelectronic structure; a first dielectric layer having a first portion extending over the semiconductor base substrate and a second portion extending from the first portion along a portion of the electrically conductive via; a second dielectric layer having a first portion extending over the first portion of the first dielectric layer and a second portion extending from the first portion along the second portion of the first dielectric layer; an insulating layer over the first portion of the second dielectric layer, wherein the second portion of the first dielectric layer and the second portion of the second dielectric layer are between the insulating layer and the portion of the electrically conductive via; and a bonding surface at the back side of the microelectronic structure at least partially defined by an exposed end portion of the electrically conductive via, and a nonconductive bonding layer including a surface of the second portion of the first dielectric layer, a surface of the second portion of the second dielectric layer and a surface of the insulating layer.

14 . The microelectronic structure of claim 13 , wherein the bonding surface is a direct bonding surface.

15 . The microelectronic structure of claim 13 , wherein the first dielectric layer comprises a diffusion barrier.

16 . The microelectronic structure of claim 13 , wherein the second dielectric layer comprises silicon oxide.

17 . The microelectronic structure of claim 13 , wherein the second dielectric layer comprises a different material compared to the insulating layer.

18 . The microelectronic structure of claim 13 , wherein the second dielectric layer and the insulating layer comprise the same material.

19 . The microelectronic structure of claim 13 , wherein the second dielectric layer is in direct contact with the insulating layer.

20 . The microelectronic structure of claim 13 , wherein the second dielectric layer and the insulating layer have different residue stress characteristics.

21 . The microelectronic structure of claim 13 , wherein one of the second dielectric layer or insulating layer is in tension, and the other of the second dielectric layer or the insulating layer is in compression.

22 . A bonded structure comprising:
the microelectronic structure of claim 13 ; and a second substrate having a front side and a back side, the front side including a nonconductive bonding layer and an exposed pad, wherein the nonconductive bonding layer on the front side of the second substrate is bonded to the nonconductive bonding layer on the back side of the first substrate, and wherein the exposed pad of the second substrate is bonded to the exposed end portion of the electrically conductive via.

Assignees

• Adeia Semiconductor Bonding Technologies Inc

Inventors

• Gao Guilian
• Lee Bongsub
• Fountain Jr Gaius Gillman
• Uzoh Cyprian Emeka
• Haba Belgacem
• Mirkarimi Laura Wills
• Katkar Rajesh

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title