Molded direct bonded and interconnected stack

Patent metadata

Field	Value
Publication number	US-2025246583-A1
Application number	US-202519068370-A
Country	US
Kind code	A1
Filing date	Mar 3, 2025
Priority date	Jul 6, 2018
Publication date	Jul 31, 2025
Grant date	—

Abstract

Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.

First claim

1 . (canceled)

2 . A microelectronic assembly, comprising:
a plurality of adjacent stacks of multiple microelectronic elements, each stack comprising:
a first substrate having a first microelectronic circuit element in the first substrate;
a second substrate having a second microelectronic circuit element in the second substrate, the second substrate hybrid bonded to the first substrate, electrically coupling the first substrate to the second substrate without adhesive; and
a first encapsulant covering at least a side edge of the second substrate facing a side edge of an adjacent stack;
a base substrate, the plurality of stacks attached to the base substrate, the plurality of stacks laterally spaced from one another; and a second encapsulant disposed in the lateral space between the plurality of adjacent stacks.

3 . The microelectronic assembly of claim 2 , wherein the second encapsulant has a different composition than the first encapsulant.

4 . The microelectronic assembly of claim 3 , wherein the second encapsulant comprises an organic material.

5 . The microelectronic assembly of claim 2 , wherein the first encapsulant comprises multiple layers of encapsulating material.

6 . The microelectronic assembly of claim 5 , wherein a first layer of the first encapsulant covers the side edge of the second substrate, and wherein a second layer of the first encapsulant is disposed adjacent to the first layer.

7 . The microelectronic assembly of claim 6 , wherein the second layer of the first encapsulant comprises silica.

8 . The microelectronic assembly of claim 2 , each stack further comprising:
a third substrate bonded over the second substrate without an intervening adhesive.

8 . The microelectronic assembly of claim 8 , at least one stack further comprising:
a first conductive via electrically coupled to the first microelectronic circuit element of the first substrate and extending at least partially through the first substrate providing electrical connectivity from the first substrate to the second substrate.

10 . The microelectronic assembly of claim 9 , wherein the base substrate comprises conductive features providing electrical connectivity from the base substrate to the second substrate.

11 . The microelectronic assembly of claim 2 , wherein the first encapsulant covers the side edge of the second substrate of at least one stack, but not the first substrate of the at least one stack.

12 . The microelectronic assembly of claim 2 , wherein the second substrate of at least one stack includes an etched portion at a perimeter, forming a recess at a perimeter edge of the second substrate.

13 . The microelectronic assembly of claim 2 , wherein at least the second substrate comprises a solid-state memory device.

14 . A microelectronic assembly, comprising:
a host element with a surface; a first stack of hybrid bonded dies attached to the surface of the host element; a second stack of hybrid bonded dies attached to the surface of the host element, the second stack laterally spaced from the first stack; and a first encapsulant disposed in the lateral space between the first stack and the second stack.

15 . The microelectronic assembly of claim 14 , wherein the first encapsulant comprises an organic material.

16 . The microelectronic assembly of claim 14 , wherein each of the first and second stacks of bonded dies comprise a first die bonded to the host element, a second die and a third die directly bonded to the first die, the third die laterally spaced from the second die.

17 . The microelectronic assembly of claim 16 , further comprising a second encapsulant disposed in the lateral space between the second die and the third die in each of the first and second stacks of bonded dies.

18 . The microelectronic assembly of claim 17 , wherein the second encapsulant has a different composition than the first encapsulant.

19 . The microelectronic assembly of claim 18 , wherein the second encapsulant comprises silicon oxide.

20 . The microelectronic assembly of claim 17 , wherein the second encapsulant comprises a first layer and a second layer with a different composition than the first layer.

Assignees

• Adeia Semiconductor Bonding Technologies Inc

Inventors

• Gao Guilian
• Uzoh Cyprian Emeka
• Theil Jeremy Alfred
• Haba Belgacem
• Katkar Rajesh

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/90

  Bond pads, in general · CPC title