Semiconductor structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-2025227975-A1
Application number	US-202418618482-A
Country	US
Kind code	A1
Filing date	Mar 27, 2024
Priority date	Jan 4, 2024
Publication date	Jul 10, 2025
Grant date	—

Abstract

A method for forming a semiconductor structure is provided. The method includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a fin element, forming an isolation structure to surround the fin element, forming a dummy gate dielectric layer across the fin structure over the isolation structure, forming a dummy gate electrode layer on the dummy gate dielectric layer, partially etching the dummy gate electrode layer and the dummy gate dielectric layer to form a trench, removing the first semiconductor layers to form gaps, forming a gate stack on the remaining portion of the dummy gate electrode layer and filling the trench and the gaps.

First claim

What is claimed is:

1 . A method for forming a semiconductor structure, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a fin element; forming an isolation structure to surround the fin element; forming a dummy gate dielectric layer across the fin structure over the isolation structure; forming a dummy gate electrode layer on the dummy gate dielectric layer; partially etching the dummy gate electrode layer and the dummy gate dielectric layer to form a trench; removing the first semiconductor layers to form gaps; and forming a gate stack on a remaining portion of the dummy gate electrode layer and filling the trench and the gaps.

2 . The method for forming the semiconductor structure as claimed in claim 1 , wherein the remaining portion of the dummy gate electrode layer has a top surface that is lower than a top surface of the fin element.

3 . The method for forming the semiconductor structure as claimed in claim 1 , wherein forming the gate stack on the remaining portion of the dummy gate electrode layer and filling the trench and gaps comprises:
forming interfacial layers on the second semiconductor layers; forming a gate dielectric layer over the interfacial layers; and forming a metal gate electrode layer over the gate dielectric layer.

4 . The method for forming the semiconductor structure as claimed in claim 3 , further comprising:
forming an oxide layer on the remaining portion of the dummy gate electrode layer while forming the interfacial layers.

5 . The method for forming the semiconductor structure as claimed in claim 1 , wherein the remaining portion of the dummy gate electrode layer protects the isolation structure from being recessed.

6 . The method for forming the semiconductor structure as claimed in claim 1 , wherein the remaining portion of the dummy gate electrode has a convex top surface.

7 . The method for forming the semiconductor structure as claimed in claim 1 , further comprising:
recessing the isolation structure to form a recess between the remaining portion of the dummy gate electrode and the fin element, wherein the gate stack further fills the recess.

8 . The method for forming the semiconductor structure as claimed in claim 7 , wherein the gate stack includes a gate dielectric layer, and in a plan view, the gate dielectric layer surrounds the remaining portion of the dummy gate electrode layer.

9 . The method for forming the semiconductor structure as claimed in claim 1 , wherein after removing the first semiconductor layers to form gaps, a remaining portion of the dummy gate dielectric layer remains between the remaining portion of the dummy gate electrode layer and the isolation structure.

10 . A method for forming a semiconductor structure, comprising:
forming a plurality of first active regions in a first region of the substrate; forming an isolation structure to surround lower portions of the plurality of first active regions; forming a first dummy gate structure over the plurality of first active regions; etching the first dummy gate structure, wherein a remaining portion of the first dummy gate structure is provided on the isolation structure; patterning upper portions of the plurality of first active regions to form a plurality of first nanostructures; and forming a first gate stack to surround the plurality of first nanostructures.

11 . The method for forming the semiconductor structure as claimed in claim 10 , wherein the first gate stack is formed on the remaining portion of the first dummy gate structure.

12 . The method for forming the semiconductor structure as claimed in claim 10 , further comprising:
forming a plurality of second active regions in a second region of the substrate, wherein a first spacing between adjacent two of the first active regions is less than a second spacing between adjacent two of the second active regions; forming the isolation structure to surround lower portions of the plurality of second active regions; forming a second dummy gate structure over the plurality of second active regions; etching the second dummy gate structure to expose the isolation structure; and patterning the plurality of second active regions to form a plurality of second nanostructures; and forming a second gate stack to surround the plurality of second nanostructures.

13 . The method for forming the semiconductor structure as claimed in claim 12 , wherein after etching the first dummy gate structure and etching the second dummy gate structure, a top surface of a first portion of the isolation structure in the first region is higher than a top surface of a second portion of the isolation structure in the second region.

14 . The method for forming the semiconductor structure as claimed in claim 10 , wherein the first dummy gate structure includes a dummy gate dielectric layer and a dummy gate electrode layer over the dummy gate dielectric layer, and etching the first dummy gate structure comprises:
etching the dummy gate electrode layer to expose a first portion of the dummy gate dielectric layer while a second portion of the dummy gate dielectric layer remains covered by the dummy gate electrode layer; and etching the first portion of the dummy gate dielectric layer to expose the plurality of first active regions.

15 . A semiconductor structure, comprising:
a plurality of nanostructures over a fin element; an isolation structure surrounding the fin element; a protection feature over the isolation structure and surrounding the fin element; and a gate stack over the protection feature and wrapping around the plurality of nanostructures.

16 . The semiconductor structure as claimed in claim 15 , wherein the protection feature comprises a semiconductor layer and a dielectric layer between the isolation structure and the semiconductor layer.

17 . The semiconductor structure as claimed in claim 16 , wherein the semiconductor layer has a curved top surface facing the gate stack.

18 . The semiconductor structure as claimed in claim 16 , wherein the dielectric layer is interposed between the semiconductor layer and the fin element.

19 . The semiconductor structure as claimed in claim 15 , further comprising:
gate spacer layers along sidewalls of the gate stack and sidewalls of the protection feature.

20 . The semiconductor structure as claimed in claim 15 , further comprising:
a source/drain feature on the fin element; and an interlayer dielectric layer over the source/drain feature, wherein a top surface of a first portion of the isolation structure directly under the interlayer dielectric layer is lower than a top surface of a second portion of the isolation structure directly under the protection feature.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chou Hung-Ju
• Lee Wei-Yang
• Peng Yuan-Ching

Classifications

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D30/014

  of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title