Multi version library cell handling and integrated circuit structures fabricated therefrom

Patent metadata

Field	Value
Publication number	US-2025225306-A1
Application number	US-202519090107-A
Country	US
Kind code	A1
Filing date	Mar 25, 2025
Priority date	Sep 20, 2017
Publication date	Jul 10, 2025
Grant date	—

Abstract

Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a fin along a first direction; a first metal line, a second metal line and a third metal line along a second direction, the second direction orthogonal to the first direction, the first metal line having a first side and a second side, the second metal line having a first side and a second side, the first side of the second metal line laterally spaced apart from the second side of the first metal line, and the third metal line having a first side and a second side, the first side of the third metal line laterally spaced apart from the second side of the second metal line, wherein the first metal line, the second metal line and the third metal line define a footprint vertically over the fin; and a first gate line and a second gate line along the second direction, the first gate line having a first side and a second side, and the second gate line having a first side and a second side, the first side of the second gate line laterally spaced apart from the second side of the first gate line, and the first gate line and the second gate line vertically over the fin and below the first metal line, the second metal line and the third metal line, wherein the first gate line and the second gate line but no additional gate lines are in the footprint of the first metal line, the second metal line and the third metal line, wherein the first gate line and the second gate line have a pitch greater than a pitch of the first metal line, the second metal line and the third metal line, wherein the first side of the first metal line is in vertical alignment with the first side of the first gate line, wherein the first side of the second metal line is in vertical alignment with a region between the second side of the first gate line and the first side of the second gate line, and wherein the second side of the third metal line is in vertical alignment with a region laterally spaced apart from the second side of the second gate line.

2 . The integrated circuit structure of claim 1 , wherein the footprint is defined in a cross-sectional view.

3 . The integrated circuit structure of claim 1 , further comprising:
a third gate line along the second direction, wherein the region laterally spaced apart from the second side of the second gate line is between the second gate line and the third gate line.

4 . The integrated circuit structure of claim 1 , further comprising:
a fourth metal line along the first direction, the fourth metal line vertically above the first gate line and the second gate line and vertically below the first metal line, the second metal line and the third metal line.

5 . The integrated circuit structure of claim 4 , wherein there are no other metal lines vertically between the fourth metal line and the first and second gate lines.

6 . The integrated circuit structure of claim 4 , wherein there are no other metal lines vertically between the fourth metal line and the first, second and third metal lines.

7 . The integrated circuit structure of claim 4 , further comprising:
a gate contact coupling the fourth metal line to one of the first gate electrode or the second gate electrode at a location vertically over the fin.

8 . The integrated circuit structure of claim 1 , wherein the first gate line and the second gate line are on a top and along a pair of sidewalls of the fin.

9 . An integrated circuit structure, comprising:
a three-dimensional body along a first direction; a first metal line, a second metal line and a third metal line along a second direction, the second direction orthogonal to the first direction, the first metal line having a first side and a second side, the second metal line having a first side and a second side, the first side of the second metal line laterally spaced apart from the second side of the first metal line, and the third metal line having a first side and a second side, the first side of the third metal line laterally spaced apart from the second side of the second metal line; and a first gate line and a second gate line along the second direction, the first gate line having a first side and a second side, and the second gate line having a first side and a second side, the first side of the second gate line laterally spaced apart from the second side of the first gate line, and the first gate line and the second gate line vertically over the three-dimensional body and below the first metal line, the second metal line and the third metal line, wherein a distance along the first direction from the first side of the first gate line to the second side of the second gate line is less than a distance along the first direction from the first side of the first metal line to the second side of the third metal line, and wherein the first gate line and the second gate line have a pitch greater than a pitch of the first metal line, the second metal line and the third metal line, wherein the first side of the first metal line is in vertical alignment with the first side of the first gate line, wherein the first side of the second metal line is in vertical alignment with a region between the second side of the first gate line and the first side of the second gate line, and wherein the second side of the third metal line is in vertical alignment with a region laterally spaced apart from the second side of the second gate line.

10 . The integrated circuit structure of claim 9 , further comprising:
a third gate line along the second direction, wherein the region laterally spaced apart from the second side of the second gate line is between the second gate line and the third gate line.

11 . The integrated circuit structure of claim 9 , further comprising:
a fourth metal line along the first direction, the fourth metal line vertically above the first gate line and the second gate line and vertically below the first metal line, the second metal line and the third metal line.

12 . The integrated circuit structure of claim 11 , further comprising:
a gate contact coupling the fourth metal line to one of the first gate electrode or the second gate electrode at a location vertically over the three-dimensional body.

13 . A method of fabricating an integrated circuit structure, the method comprising:
forming a fin along a first direction; forming a first metal line, a second metal line and a third metal line along a second direction, the second direction orthogonal to the first direction, the first metal line having a first side and a second side, the second metal line having a first side and a second side, the first side of the second metal line laterally spaced apart from the second side of the first metal line, and the third metal line having a first side and a second side, the first side of the third metal line laterally spaced apart from the second side of the second metal line, wherein the first metal line, the second metal line and the third metal line define a footprint vertically over the fin; and forming a first gate line and a second gate line along the second direction, the first gate line having a first side and a second side, and the second gate line having a first side and a second side, the first side of the second gate line laterally spaced apart from the second side of the first gate line, and the first gate line and the second gate line vertically over the fin and below the first metal line, the second metal line and the third metal line, wherein the first gate line and the second gate line but no additional gate lines are in the footprint of the first metal line, the second metal line and the third metal line, wherein the first gate line and t

Assignees

• Intel Corp

Inventors

• Kumar Ranjith
• Shi Quan
• Bohr Mark T
• Yeoh Andrew W
• Chakravarty Sourav
• Chappell Barbara A
• Webb M Clair

Classifications

• H10D84/975

  Wiring regions or routing · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D84/907 Primary

  CMOS gate arrays · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• G06F30/3947

  global · CPC title