FINFET Device with Wrapped-Around Epitaxial Structure and Manufacturing Method Thereof

Patent metadata

Field	Value
Publication number	US-2025169159-A1
Application number	US-202519029882-A
Country	US
Kind code	A1
Filing date	Jan 17, 2025
Priority date	Aug 28, 2017
Publication date	May 22, 2025
Grant date	—

Abstract

A semiconductor device includes a substrate, an isolation feature disposed on the substrate, first and second fins protruding from the substrate and upwardly through the isolation feature, and a gate stack engaging each of the fins. The semiconductor device also includes a first epitaxial layer having a first portion over top and sidewall surfaces of S/D regions of the first fin and a second portion over top and sidewall surfaces of S/D regions of the second fin, a second epitaxial layer having a first portion over top and sidewall surfaces of the first portion of the first epitaxial layer and a second portion over top and sidewall surfaces of the second portion of the first epitaxial layer. The first and second portions of the second epitaxial layer are spaced apart. Each of the first and second portions of the second epitaxial layer is in physical contact with the isolation feature.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate; an isolation feature disposed on the substrate; first and second fins protruding from the substrate and upwardly through the isolation feature, wherein each fin includes two source/drain (S/D) regions and a channel region; a gate stack engaging each fin at the respective channel region; a first epitaxial layer having a first portion over top and sidewall surfaces of the S/D regions of the first fin and a second portion over top and sidewall surfaces of the S/D regions of the second fin; a second epitaxial layer having a first portion over top and sidewall surfaces of the first portion of the first epitaxial layer and a second portion over top and sidewall surfaces of the second portion of the first epitaxial layer, wherein the first and second portions of the second epitaxial layer are spaced apart, wherein each of the first and second portions of the second epitaxial layer is in physical contact with the isolation feature; and a contact feature disposed over the second epitaxial layer.

2 . The semiconductor device of claim 1 , further comprising:
gate spacers disposed on sidewalls of the gate stack, wherein the gate spacers separate the first and second epitaxial layers from physically contacting the gate stack.

3 . The semiconductor device of claim 2 , further comprising:
a dielectric layer disposed above the channel regions of the first and second fins and directly under both the gate spacers and the gate stack, wherein the dielectric layer is in physical contact with the first epitaxial layer.

4 . The semiconductor device of claim 3 , wherein the gate spacers comprise a nitride, and the dielectric layer comprises an oxide.

5 . The semiconductor device of claim 1 , wherein each of the first and second fins includes a top surface that remains flat across the respective S/D regions and the respective channel region.

6 . The semiconductor device of claim 1 , wherein the first and second portions of the first epitaxial layer are spaced apart.

7 . The semiconductor device of claim 1 , wherein the contact feature is disposed over top and sidewall surfaces of the first portion of the second epitaxial feature and over top and sidewall surfaces of the second portion of the second epitaxial feature.

8 . The semiconductor device of claim 1 , wherein a portion of the contact feature laterally stacked between the first and second portions of the second epitaxial feature is in physical contact with the isolation feature.

9 . The semiconductor device of claim 1 , further comprising:
a germano-silicide layer disposed vertically between the contact feature and the second epitaxial layer.

10 . The semiconductor device of claim 1 , further comprising:
an interlayer-dielectric (ILD) layer disposed on sidewalls of the contact feature, wherein a top surface of the ILD layer and a top surface of the contact feature are coplanar.

11 . A semiconductor device comprising:
a substrate; an isolation structure over the substrate; first and second fins extending from the substrate and through the isolation structure, wherein each fin includes a channel region and two source/drain (S/D) regions sandwiching the channel region; a gate stack engaging each fin at the respective channel region; a first epitaxial layer over top and sidewall surfaces of the S/D regions of the first and second fins, the first epitaxial layer extending continuously from a position above the first fin to a position above the second fin; and a second epitaxial layer over top and sidewall surfaces of the first epitaxial layer, wherein a portion of the second epitaxial layer laterally between the first and second fins is directly under a bottom surface of the first epitaxial layer.

12 . The semiconductor device of claim 11 , wherein each fin has a substantially flat top surface extending from the channel region to the respective S/D regions.

13 . The semiconductor device of claim 11 , further comprising:
a contact feature disposed over top and sidewall surfaces of the second epitaxial layer; and an interlayer-dielectric (ILD) layer disposed on sidewalls of the contact feature.

14 . The semiconductor device of claim 13 , wherein the contact feature is in physical contact with the isolation structure.

15 . The semiconductor device of claim 13 , wherein, in a cross section perpendicular to a lengthwise direction of the first fin, the contact feature separates the ILD layer from physically contacting the second epitaxial layer.

16 . The semiconductor device of claim 13 , further comprising:
a dielectric residue disposed under a bottom surface of the second epitaxial layer and separated from the ILD layer by the contact feature, wherein the dielectric residue and the ILD layer have a same material composition.

17 . A semiconductor device comprising:
a substrate; an isolation structure over the substrate; a fin extending from the substrate and through the isolation structure; a metal gate stack over a channel region of the fin; an epitaxial layer over top and sidewall surfaces of a source/drain (S/D) region of the fin; a gate spacer disposed on a sidewall of the metal gate stack, wherein the gate spacer separates the metal gate stack from physically contacting the epitaxial layer; a dielectric layer directly under the gate spacer and the metal gate stack, wherein the epitaxial layer physically contacts the dielectric layer; and a conductive feature disposed over and in electrical coupling with the epitaxial layer, wherein the conductive feature physically contacts the isolation structure.

18 . The semiconductor device of claim 17 , wherein the epitaxial layer is a first epitaxial layer, the semiconductor device further comprising:
a second epitaxial layer over top and sidewall surfaces of the first epitaxial layer, wherein the gate spacer separates the second epitaxial layer from physically contacting the dielectric layer.

19 . The semiconductor device of claim 18 , further comprising:
an interlayer-dielectric (ILD) layer disposed over the isolation structure, wherein the second epitaxial layer separates the first epitaxial layer from the ILD layer.

20 . The semiconductor device of claim 17 , wherein a top surface of the fin in the channel region and the S/D region is substantially flat.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Cheng-Yu
• Yu Chia-Ta
• LEE Kai-Hsuan
• Yeong Sai-Hooi
• Yang Feng-Cheng

Classifications

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D30/6219 Primary

  characterised by the source or drain electrodes · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title