Array substrate, display panel and display apparatus

Patent metadata

Field	Value
Publication number	US-2025151504-A1
Application number	US-202519017860-A
Country	US
Kind code	A1
Filing date	Jan 13, 2025
Priority date	Dec 16, 2022
Publication date	May 8, 2025
Grant date	—

Abstract

An array substrate includes a base substrate, a first conductive layer, a first electrode, an organic planarization layer and an organic active layer. The first conductive layer is provided on a side of the base substrate. The first electrode is provided on a side of the first conductive layer away from the base substrate, an orthographic projection of the first electrode on the base substrate overlapping an orthographic projection of the drain electrode on the base substrate. The organic planarization layer is provided on a side of the first electrode away from the base substrate, first via holes being provided in the organic planarization layer. The organic active layer is provided on a side of the organic planarization layer away from the base substrate, the organic active layer being connected to the source electrode by a first via hole and connected to the drain electrode by a first via hole.

First claim

What is claimed is:

1 . An array substrate, comprising:
a base substrate; a first conductive layer disposed on a side of the base substrate, the first conductive layer comprising a source electrode and a drain electrode; a first electrode disposed on a side of the first conductive layer away from the base substrate, an orthographic projection of the first electrode on the base substrate being overlapped with an orthographic projection of the drain electrode on the base substrate; an organic planarization layer disposed on a side of the first electrode away from the base substrate, the organic planarization layer being provided with first via holes, and the first via holes being connected to the source electrode and the drain electrode, respectively; an organic active layer disposed on a side of the organic planarization layer away from the base substrate, the organic active layer being connected to the source electrode through the first via hole and connected to the drain electrode through the first via hole.

2 . The array substrate according to claim 1 , wherein an angle between a hole wall of the first via hole and a face of the first conductive layer away from the base substrate is less than or equal to 70°.

3 . The array substrate according to claim 1 , wherein an area of the organic planarization layer corresponding to a display area of a sub-pixel is provided with an opening portion.

4 . The array substrate according to claim 3 , wherein an orthographic projection of the display area on the base substrate is within an orthographic projection of the opening portion on the base substrate.

5 . The array substrate according to claim 1 , further comprising:
a gate insulating layer set disposed on a side of the organic active layer away from the base substrate, an orthographic projection of the gate insulating layer set on the base substrate being overlapped with an orthographic projection of the organic active layer on the base substrate; a first gate electrode layer disposed on a side of the gate insulating layer set away from the base substrate, the first gate electrode layer comprising a first gate electrode.

6 . The array substrate according to claim 5 , wherein the gate insulating layer set comprises:
a first gate insulating layer disposed on a side of the organic active layer away from the base substrate; a second gate insulating layer disposed on a side of the first gate insulating layer away from the base substrate, performance of the second gate insulating layer blocking an etching solution of the first gate electrode layer being stronger than performance of the first gate insulating layer blocking an etching solution of the first gate electrode layer.

7 . The array substrate according to claim 5 , wherein an orthographic projection of the first gate electrode on the base substrate is within an orthographic projection of the organic active layer on the base substrate.

8 . The array substrate according to claim 7 , wherein the organic active layer comprises a conductor portion, and an orthographic projection of the conductor portion on the base substrate is not overlapped with the orthographic projection of the first gate electrode on the base substrate.

9 . The array substrate according to claim 8 , wherein in the first direction, a distance between two first via holes of a thin film transistor is larger than a width of the first gate electrode.

10 . The array substrate according to claim 5 , further comprising:
a passivation layer disposed on a side of the first gate electrode layer away from the base substrate; a second electrode layer disposed on a side of the passivation layer away from the base substrate.

11 . The array substrate according to claim 10 , further comprising:
a second gate electrode layer disposed between the passivation layer and the second electrode layer, wherein the second gate electrode layer comprises a second gate electrode and a second gate line, the second gate electrode is connected to the first gate electrode, the second gate line extends along a first direction, the second gate line is connected to a plurality of second gate electrodes disposed along the first direction, and the first direction is parallel to a face of the base substrate close to the first conductive layer.

12 . The array substrate according to claim 5 , wherein the first gate electrode layer further comprises a first gate line, the first gate line extends along a first direction, the first gate line is connected to a plurality of first gate electrodes disposed along the first direction, and the first direction is parallel to a face of the base substrate close to the first conductive layer.

13 . The array substrate according to claim 10 , further comprising:
a protective layer covering at least a sidewall of the organic active layer.

14 . The array substrate according to claim 13 , wherein the protective layer is disposed between the gate insulating layer set and the first gate electrode, and between the organic planarization layer and the passivation layer, and covers sidewalls of the organic active layer and the gate insulating layer set.

15 . The array substrate according to claim 13 , wherein the protective layer is disposed between the first gate electrode layer and the organic planarization layer and the passivation layer, and covers sidewalls of the organic active layer, the gate insulating layer set, and the first gate electrode, and compatibility between the protective layer and the organic active layer is stronger than compatibility between the passivation layer and the organic active layer.

16 . The array substrate according to claim 1 , wherein a work function of the first conductive layer is greater than 4.5 eV.

17 . The array substrate according to claim 1 , wherein the array substrate is a flexible array substrate.

18 . A display panel, comprising:
an array substrate according to claim 1 ; a color film substrate disposed opposite to the array substrate; a liquid crystal layer disposed between the array substrate and the color film substrate.

19 . The display panel according to claim 18 , wherein the array substrate is a flexible array substrate, and the color film substrate is a flexible color film substrate.

20 . A display apparatus, comprising: a display panel according to claim 18 , the display apparatus being a rollable display apparatus, a foldable display apparatus or a curved display apparatus.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Yuan Guangcai
• Hu hehe
• Hsieh Changhan
• Yang Wei
• Dong Liwen
• He Jiayu
• Hou Dongfei
• Zhang Zhen
• Ning ce
• Gu Xin
• Li Zhengliang

Classifications

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10K59/123

  Connection of the pixel electrodes to the thin film transistors [TFT] · CPC title

• H10K59/124

  Insulating layers formed between TFT elements and OLED elements · CPC title

• H10K19/10

  comprising field-effect transistors · CPC title