Multi-die integrated package design method and system using the same

Patent metadata

Field	Value
Publication number	US-2025139349-A1
Application number	US-202318399154-A
Country	US
Kind code	A1
Filing date	Dec 28, 2023
Priority date	Nov 1, 2023
Publication date	May 1, 2025
Grant date	—

Abstract

A multi-chip integrated package design system includes a model analysis, a 3D model analysis and an electrical simulation. The model analysis obtains a pin connection mode of the designed circuit according to a designed circuit, obtains at least one conductive layer of the designed circuit according to a layer stackup, selects a transmission line model that meets the pin connection mode and at least one conductive layer, substitutes the layer stackup and a design rule into the selected transmission line model to generate an equivalent circuit, generates a corresponding relationship according to the equivalent circuit, and obtains the transmission line length corresponding to a parameter design target according to the corresponding relationship. The 3D model analysis constructs a 3D model of the designed circuit according to the obtained the transmission line length. The electrical simulation determines whether the characteristic parameter of the 3D model meets the parameter design target.

First claim

What is claimed is:

1 . A multi-chip integrated package design method, comprising:
obtaining a schematic of a design circuit; performing a circuit layout according to the schematic of the design circuit; constructing a three-dimensional (3D) model of the circuit layout; determining whether a characteristic parameter of the 3D model meets a characteristic parameter design target; select a patent document that meets the circuit layout from a patent database when the characteristic parameter does not meet the characteristic parameter design target; and optimizing the design circuit according to the patent document; wherein performing the circuit layout according to the schematic of the design circuit comprises:
obtaining a pin connection mode of the design circuit according to the schematic of the design circuit;
obtaining at least one conductive layer of the design circuit according to the layer stackup;
selecting a transmission line model that meets the pin connection mode and the at least one conductive layer from a plurality of the transmission line models in a transmission line model database;
generating an equivalent circuit by substituting the layer stackup and a design rule into the selected transmission line model;
generating a corresponding relationship between a transmission line length and the characteristic parameter according to the equivalent circuit;
obtaining the transmission line length corresponding to the characteristic parameter design target according to the corresponding relationship of the transmission line length and the characteristic parameter, wherein the transmission line length is used as a design constraint for the circuit layout; and
wherein constructing the 3D model of the circuit layout comprises:
performing the circuit layout of the design circuit according to the obtained the transmission line length used as the design constraint and construct the 3D model of the circuit layout.

2 . The multi-chip integrated package design method according to claim 1 , wherein selecting the patent document that meets the circuit layout from the patent database when the characteristic parameter does not meet the characteristic parameter design target comprises:
when the characteristic parameter does not meet the characteristic parameter design target, selecting the patent document that meets the circuit layout from the patent database by using a technology/efficiency/target matrix and placing a structure disclosed in the patent document into the 3D model of the circuit layout.

3 . The multi-chip integrated package design method according to claim 1 , wherein the characteristic parameter VL is a voltage amplitude loss; the multi-chip integrated package design method further comprises:
comprising the voltage amplitude loss according to following formula (1);

VL
=

10

S
⁢
21
⁢

(

f
0

)

20

;

(
1
)

wherein f 0 represents an input signal frequency, and S 21 represents an insertion loss of a S parameter.

4 . The multi-chip integrated package design method according to claim 3 , further comprises:
obtaining the voltage amplitude losses of different numbers of the equivalent circuits connected in series to build a corresponding relationship between a transmission line length and the voltage amplitude loss.

5 . The multi-chip integrated package design method according to claim 1 , wherein the characteristic parameter is an insertion loss; the multi-chip integrated package design method further comprising:
obtaining the characteristic parameter design target IL I according to following formula (2);

IL
I

=

20
×

log
⁡
(

V
out

V
in

)

(
2
)

wherein V out represents an output voltage, and V in represents an input voltage.

6 . The multi-chip integrated package design method according to claim 5 , further comprising:
obtaining the insertion losses of different numbers of the equivalent circuits connected in series to build a corresponding relationship between the transmission line length and the insertion loss.

7 . The multi-chip integrated package design method according to claim 5 , wherein the characteristic parameter is a return loss; the multi-chip integrated package design method further comprising:
obtaining the characteristic parameter design target RL according to following formula;

RL
=

-
20

×
log
⁢

❘
"\[LeftBracketingBar]"

Γ

❘
"\[RightBracketingBar]"

wherein a reflection coefficient Γ=(Z L −Z O )/(Z L +Z O ), wherein Z L represents a characteristic impedance of the transmission line, and Z O represents a characteristic impedance of a signal source.

8 . The multi-chip integrated package design method according to claim 7 , further comprising:
obtaining the return loss of different numbers of the equivalent circuits connected in series to build a corresponding relationship between the transmission line length and the return loss.

9 . A multi-chip integrated packaging design system, comprising:
a model analysis configured to:
obtain a schematic of a design circuit; and
perform a circuit layout according to the schematic of the design circuit;
a 3D model analysis configured to:
construct a 3D model of the circuit layout;
an electrical simulation configured to:
determine whe

Assignees

• Ind Tech Res Inst

Inventors

• Hsu Chien-Min
• Lin Chang-Tzu
• Wu Shih-Hsien

Classifications

• G06F2113/18

  Chip packaging · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/31 Primary

  Design entry, e.g. editors specifically adapted for circuit design · CPC title