Floating point bias switching

Patent metadata

Field	Value
Publication number	US-2025130774-A1
Application number	US-202318395190-A
Country	US
Kind code	A1
Filing date	Dec 22, 2023
Priority date	Oct 20, 2023
Publication date	Apr 24, 2025
Grant date	—

Abstract

The disclosed circuit can interpret a bit sequence as a value based on one of multiple floating point number formats in a bias mode indicated by a bias mode indicator. The circuit can and perform an operation using the value in the bias mode. Various other methods, systems, and computer-readable media are also disclosed.

First claim

What is claimed is:

1 . A device comprising:
a processing circuit configured to:
interpret a bit sequence as a value based on one of a plurality of number formats as indicated by a bias mode indicator; and
perform an operation using the value.

2 . The device of claim 1 , wherein the bias mode indicator corresponds to a status bit.

3 . The device of claim 2 , wherein the status bit is hardware programmable.

4 . The device of claim 2 , wherein the status bit is dynamically adjustable via software.

5 . The device of claim 1 , further comprising a plurality of processing circuits that includes the processing circuit, wherein each of the plurality of processing circuits correspond to a respective one of the plurality of number formats.

6 . The device of claim 1 , wherein the processing circuit is configured to interpret an exponent using a bias in accordance with the corresponding number format and further based on the bias mode indicator.

7 . The device of claim 1 , wherein the processing circuit is configured to interpret special bit sequences as special values in accordance with the corresponding number format.

8 . The device of claim 1 , further comprising a set of instructions and a corresponding bias mode indicator for each of the plurality of number formats.

9 . The device of claim 8 , wherein each set of instructions is configured to interpret an exponent using a bias in accordance with the corresponding number format and further based on the corresponding bias mode indicator.

10 . The device of claim 8 , wherein each set of instructions is configured to interpret special bit sequences as special values in accordance with the corresponding number format.

11 . The device of claim 1 , wherein each of the plurality of number formats correspond to a floating point format.

12 . The device of claim 11 , wherein each of the floating point formats have a similar level of precision.

13 . A system comprising:
a memory; and a processing circuit configured with a set of instructions, wherein:
each instruction is configured to interpret a bit sequence read from the memory as a value based on one of a plurality of number formats as modified by a bias mode indicator; and
the processing circuit is configured to perform an operation using the value.

14 . The system of claim 13 , wherein the bias mode indicator is dynamically adjustable.

15 . The system of claim 13 , wherein the set of instructions is configured to interpret an exponent in accordance with the corresponding number format using a bias based on the bias mode indicator.

16 . The system of claim 13 , wherein each set of instructions is configured to interpret special bit sequences as special values in accordance with the corresponding number format using a bias based on the bias mode indicator.

17 . The system of claim 13 , wherein each of the plurality of number formats correspond to a floating point format, each of the floating point formats having a similar level of precision.

18 . A method comprising:
receiving, as part of an operation, a bit sequence corresponding to a number format; extracting a number element from the bit sequence based on the number format; applying a bias to the extracted element based on a bias mode indicator to determine a value from the bit sequence; and completing the operation using the determined value.

19 . The method of claim 18 , wherein the bias mode indicator is dynamically adjustable.

20 . The method of claim 18 , wherein the number format corresponds to a floating point format and the number element corresponds to an exponent.

Assignees

• Advanced Micro Devices Inc

Inventors

• Shah Shubh
• Garg Ashutosh
• He Bin
• Mantor Michael
• Marwaha Shubra
• Maiyuran Subramaniam

Classifications

• G06F7/556 Primary

  Logarithmic or exponential functions · CPC title

• G06F7/483 Primary

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title