Processor and control method of processor

Patent metadata

Field	Value
Publication number	US-9477442-B2
Application number	US-201414479392-A
Country	US
Kind code	B2
Filing date	Sep 8, 2014
Priority date	Mar 30, 2012
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

A processor includes: an exponent generating unit that generates an exponent part of a coefficient represented by a floating point number format based on a first part of received input data, the coefficient being obtained when an exponential function is decomposed into a series operation and the coefficient for the series operation; a storage unit that stores a mantissa part of the coefficient; a constant generating unit that reads constant data corresponding to a second part of the input data from the storage unit; and a selecting unit that selects and outputs the constant data from the constant generating unit when an instruction to be executed is a coefficient calculation instruction for calculation of the coefficient of the exponential function.

First claim

What is claimed is:

1. A processor comprising:
an exponent generating unit that generates an exponent part of a coefficient represented by a floating point number format based on a first part of received input data, the coefficient being obtained when an exponential function is decomposed into a series operation and the coefficient for the series operation;
a storage unit that stores a mantissa part of the coefficient;
a constant generating unit that reads constant data corresponding to a second part of the input data from the storage unit; and
a selecting unit that selects and outputs the constant data from the constant generating unit when an instruction to be executed is a coefficient calculation instruction for calculation of the coefficient of the exponential function.

2. The processor according to claim 1 , wherein, as the constant data, the storage unit stores a mantissa part which is obtained when a value of (2**(i/(2** a bit width of the second part)))(** represents exponentiation) is represented by the floating point number format, in correspondence with a value i (i is a natural number) indicated by the second part of the input data.

3. The processor according to claim 2 , wherein the first part of the input data is an (n +11) th bit to an (n +1) th bit (n is a natural number) of the input data, and wherein the second part of the input data is an n th bit to a 0 th bit of the input data.

4. The processor according to claim 3 , wherein the (n +11) th bit to the (n +1) th bit of the input data correspond to the exponent part of the coefficient represented by the floating point number format, and the n th bit to the 0 th bit of the input data correspond to the mantissa part of the coefficient represented by the floating point number format.

5. The processor according to claim 1 , comprising a product-sum arithmetic unit that performs a product-sum operation using the input data,
wherein, when the instruction to be executed is an instruction other than the coefficient calculation instruction, a product-sum operation result from the product-sum arithmetic unit that is a result of the product-sum operation using the input data is selected and output.

6. A control method of a processor, comprising:
generating, by an exponent generating unit of the processor, an exponent part of a coefficient represented by a floating point number format based on a first part of received input data, the coefficient being obtained when an exponential function is decomposed into a series operation and the coefficient for the series operation;
reading, by a constant generating unit of the processor, constant data corresponding to a second part of the input data from a storage unit that stores a mantissa part of the coefficient; and
selecting and outputting, by a selecting unit of the processor, the constant data from the constant generating unit when an instruction to be executed is a coefficient calculation instruction for calculation of the coefficient of the exponential function.

Assignees

• Fujitsu Ltd

Inventors

• Hondo Mikio

Classifications

• G06F7/483

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title

• G06F7/556 Primary

  Logarithmic or exponential functions · CPC title

• G06F2207/556

  Indexing scheme relating to group G06F7/556 · CPC title

• G06F2207/483

  Indexing scheme relating to group G06F7/483 · CPC title