Semiconductor device

Patent metadata

Field	Value
Publication number	US-2025118357-A1
Application number	US-202418892187-A
Country	US
Kind code	A1
Filing date	Sep 20, 2024
Priority date	Oct 6, 2023
Publication date	Apr 10, 2025
Grant date	—

Abstract

Provided is a semiconductor device including a substrate, a first transistor on the substrate, an interlayer insulating layer covering the first transistor, a second transistor on the interlayer insulating layer, and a storage node contact passing through the interlayer insulating layer, and connecting any one of source/drain electrodes of the first transistor and a gate electrode of the second transistor, wherein a first channel pattern of the first transistor may include an n-type oxide transistor, and a second channel pattern of the second transistor may include an p-type oxide transistor.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate; a first transistor on the substrate; an interlayer insulating layer covering the first transistor; a second transistor on the interlayer insulating layer; and a storage node contact passing through the interlayer insulating layer, and connecting any one of source/drain electrodes of the first transistor and a gate electrode of the second transistor, wherein:
a first channel pattern of the first transistor includes an n-type oxide transistor; and
a second channel pattern of the second transistor includes an p-type oxide transistor.

2 . The semiconductor device of claim 1 , wherein the first channel pattern and the second channel pattern vertically overlap each other.

3 . The semiconductor device of claim 1 , wherein the first transistor comprises a first gate electrode on the substrate, a first insulating layer on the first gate electrode, the first channel pattern on the first insulating layer, and first and second source/drain electrodes, wherein the first and second source/drain electrodes are spaced apart in a first direction parallel to the substrate.

4 . The semiconductor device of claim 1 , wherein the second transistor comprises a second gate electrode on the interlayer insulating layer, a second insulating layer on the second gate electrode, the second channel pattern on the second insulating layer, and third and fourth source/drain electrodes, wherein the third and fourth source/drain electrodes are spaced apart in the first direction.

5 . The semiconductor device of claim 1 , wherein the first gate electrode of the first transistor and the second gate electrode of the second transistor extend in a second direction parallel to the substrate and vertically crossing the first direction.

6 . The semiconductor device of claim 2 , wherein the first and second source/drain electrodes are disposed on the first channel pattern and the first insulating layer.

7 . The semiconductor device of claim 3 , wherein the second channel pattern is disposed on the third and fourth source/drain electrodes and the second insulating layer.

8 . The semiconductor device of claim 7 , wherein the thickness of the second channel pattern is substantially uniform.

9 . The semiconductor device of claim 3 , wherein the third and fourth source/drain electrodes are disposed on the second channel pattern and the second insulating layer.

10 . The semiconductor device of claim 1 , wherein the storage node contact vertically overlaps the first channel pattern and the second channel pattern.

11 . The semiconductor device of claim 1 , wherein the second channel pattern comprises a chalcogenide material.

12 . A semiconductor device comprising:
a substrate; a first gate electrode on the substrate; a first insulating layer on the first gate electrode; a first channel pattern and first and second source/drain electrodes on the first insulating layer; a first interlayer insulating layer on the first channel pattern and the first and second source/drain electrodes; a second gate electrode on the first interlayer insulating layer; a second insulating layer on the second gate electrode; a second channel pattern and third and fourth source/drain electrodes on the second insulating layer; and a storage node contact passing through the first interlayer insulating layer, and connecting the second source/drain electrode and the second gate electrode, wherein:
the first gate electrode and the second gate electrode vertically overlap each other;
the first source/drain electrode and the third source/drain electrode vertically overlap each other;
the second source/drain electrode and the fourth source/drain electrode vertically overlap each other; and
the first channel pattern and the second channel pattern vertically overlap each other.

13 . The semiconductor device of claim 12 , wherein:
the first channel pattern comprises an n-type oxide transistor; and the second channel pattern comprises a p-type oxide transistor.

14 . The semiconductor device of claim 13 , wherein the second channel pattern comprises a chalcogenide material.

15 . The semiconductor device of claim 12 , wherein:
the first and second source/drain electrodes are spaced apart in a first direction parallel to the substrate; and the third and fourth source/drain electrodes are spaced apart in the first direction.

16 . The semiconductor device of claim 15 , wherein the first and second source/drain electrodes are disposed on the first channel pattern and the first insulating layer.

17 . The semiconductor device of claim 15 , wherein the second channel pattern is disposed on the third and fourth source/drain electrodes and the second insulating layer.

18 . The semiconductor device of claim 17 , wherein the thickness of the second channel pattern is substantially uniform.

19 . The semiconductor device of claim 15 , wherein the third and fourth source/drain electrodes are disposed on the second channel pattern and the second insulating layer.

20 . The semiconductor device of claim 12 , further comprising a second interlayer insulating layer covering the third and fourth source/drain electrodes and the second channel pattern.

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• Nam Sooji
• Cho Sung Haeng
• NA Jeho
• Sung Chihun
• Choi Kyunghee
• Han Jung Hoon

Classifications

• G11C11/4096 Primary

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• H10B12/33 Primary

  the capacitor extending under the transistor · CPC title