Semiconductor device and driving method thereof
US-2015381169-A1 · Dec 31, 2015 · US
Semiconductor-element-including memory device
US2024029775A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2024029775-A1 |
| Application number | US-202318222116-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jul 14, 2023 |
| Priority date | Jul 20, 2022 |
| Publication date | Jan 25, 2024 |
| Grant date | — |
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Abstract
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A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction in plan view on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, and in a page read operation, a first refresh operation of increasing by an impact ionization phenomenon, the number of positive holes in the semiconductor body of a memory cell for which page writing has been performed and a second refresh operation of decreasing the number of positive holes in the semiconductor body of a memory cell for which page writing has not been performed are performed and a third refresh operation for a memory cell, in a page, in which the logical “1” data is stored is performed by using latch data in a sense amplifier circuit.
First claim
Opening claim text (preview).
What is claimed is: 1 . A semiconductor-element-including memory device that is a memory device in which in plan view on a substrate, a plurality of pages are arranged in a column direction, each of the pages being constituted by a plurality of memory cells arranged in a row direction, each of the memory cells included in each of the pages comprising: a semiconductor body that stands on the substrate in a vertical direction or that extends along the substrate in a horizontal d…
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- G11C11/403Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Electricity · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US2024029775A1 cover?
- A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction in plan view on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, and in a page read operation, a first refresh operation of increasing by an impact ionization phenomenon, the numb…
- Who is the assignee on this patent?
- Unisantis Elect Singapore Pte
- What technology area does this patent fall under?
- Primary CPC classification G11C11/403. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Thu Jan 25 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).