Plugs for interconnect lines for advanced integrated circuit structure fabrication

Patent metadata

Field	Value
Publication number	US-2025098258-A1
Application number	US-202418970265-A
Country	US
Kind code	A1
Filing date	Dec 5, 2024
Priority date	Nov 30, 2017
Publication date	Mar 20, 2025
Grant date	—

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
an inter-layer dielectric (ILD) layer above a substrate, the ILD layer having a composition; a conductive interconnect structure in a trench in the ILD layer, the conductive interconnect structure having a first conductive line and a second conductive line, an end of the first conductive line laterally spaced apart and electrically isolated from an end of the second conductive line, wherein the first and second conductive lines of the conductive interconnect structure have a bottom on the ILD layer, and wherein the first and second conductive lines of the conductive interconnect structure have a top surface; and a dielectric plug between and in lateral contact with the ends of the first and second conductive lines of the conductive interconnect structure, the dielectric plug having a composition different than a composition of the ILD layer, wherein the dielectric plug has a bottom on the ILD layer and has a top surface, the top surface of the dielectric plug substantially co-planar with the top surface of the first and second conductive lines of the conductive interconnect structure.

2 . The integrated circuit structure of claim 1 , wherein the composition of the dielectric plug comprises a metal oxide material.

3 . The integrated circuit structure of claim 2 , wherein the metal oxide material is aluminum oxide.

4 . The integrated circuit structure of claim 1 , wherein the dielectric plug has an approximately vertical seam spaced approximately equally from the first conductive line of the conductive interconnect structure and from the second conductive line of the conductive interconnect structure.

5 . The integrated circuit structure of claim 1 , further comprising:
a first conductive via in a second trench in the ILD layer, the first conductive via below the bottom of the first conductive line, and the first conductive via electrically coupled to the first conductive line; and a second conductive via in a third trench in the ILD layer, the second conductive via below the bottom of the second conductive line, and the second conductive via electrically coupled to the second conductive line.

6 . The integrated circuit structure of claim 1 , wherein the first and second conductive lines of the conductive interconnect structure comprise a conductive barrier liner and a conductive fill material.

7 . A method of fabricating an integrated circuit structure, the method comprising:
forming an inter-layer dielectric (ILD) layer above a substrate, the ILD layer having a composition; forming a conductive interconnect structure in a trench in the ILD layer, the conductive interconnect structure having a first conductive line and a second conductive line, an end of the first conductive line laterally spaced apart and electrically isolated from an end of the second conductive line, wherein the first and second conductive lines of the conductive interconnect structure have a bottom on the ILD layer, and wherein the first and second conductive lines of the conductive interconnect structure have a top surface; and forming a dielectric plug between and in lateral contact with the ends of the first and second conductive lines of the conductive interconnect structure, the dielectric plug having a composition different than a composition of the ILD layer, wherein the dielectric plug has a bottom on the ILD layer and has a top surface, the top surface of the dielectric plug substantially co-planar with the top surface of the first and second conductive lines of the conductive interconnect structure.

8 . The method of claim 7 , wherein the composition of the dielectric plug comprises a metal oxide material.

9 . The method of claim 8 , wherein the metal oxide material is aluminum oxide.

10 . The method of claim 7 , wherein the dielectric plug has an approximately vertical seam spaced approximately equally from the first conductive line of the conductive interconnect structure and from the second conductive line of the conductive interconnect structure.

11 . The method of claim 7 , further comprising:
forming a first conductive via in a second trench in the ILD layer, the first conductive via below the bottom of the first conductive line, and the first conductive via electrically coupled to the first conductive line; and forming a second conductive via in a third trench in the ILD layer, the second conductive via below the bottom of the second conductive line, and the second conductive via electrically coupled to the second conductive line.

12 . The method of claim 7 , wherein the first and second conductive lines of the conductive interconnect structure comprise a conductive barrier liner and a conductive fill material.

13 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
an inter-layer dielectric (ILD) layer above a substrate, the ILD layer having a composition;
a conductive interconnect structure in a trench in the ILD layer, the conductive interconnect structure having a first conductive line and a second conductive line, an end of the first conductive line laterally spaced apart and electrically isolated from an end of the second conductive line, wherein the first and second conductive lines of the conductive interconnect structure have a bottom on the ILD layer, and wherein the first and second conductive lines of the conductive interconnect structure have a top surface; and
a dielectric plug between and in lateral contact with the ends of the first and second conductive lines of the conductive interconnect structure, the dielectric plug having a composition different than a composition of the ILD layer, wherein the dielectric plug has a bottom on the ILD layer and has a top surface, the top surface of the dielectric plug substantially co-planar with the top surface of the first and second conductive lines of the conductive interconnect structure.

14 . The computing device of claim 13 , further comprising:
a memory coupled to the board.

15 . The computing device of claim 13 , further comprising:
a communication chip coupled to the board.

16 . The computing device of claim 13 , further comprising:
a battery coupled to the board.

17 . The computing device of claim 13 , further comprising:
a camera coupled to the board.

18 . The computing device of claim 13 , further comprising:
a GPS coupled to the board.

19 . The computing device of claim 13 , wherein the component is a packaged integrated circuit die.

20 . The computing device of claim 13 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Assignees

• Intel Corp

Inventors

• Yeoh Andrew W
• Jin Ilsup
• Kandas Angelo
• Hattendorf Michael L
• Auth Christopher P

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title