Semiconductor device with layered dielectric

Patent metadata

Field	Value
Publication number	US-2025079366-A1
Application number	US-202418788588-A
Country	US
Kind code	A1
Filing date	Jul 30, 2024
Priority date	Sep 5, 2023
Publication date	Mar 6, 2025
Grant date	—

Abstract

A semiconductor device assembly with layered dielectric is disclosed. The semiconductor device assembly includes a first semiconductor die and a second semiconductor die coupled with the first semiconductor die. The second semiconductor die is at least partially surrounded by a tensile dielectric and a compressive dielectric disposed at the first semiconductor die. The tensile dielectric is configured to experience tensile stress at an upper surface and compressive stress at a lower surface (e.g., the tensile dielectric will warp concave down). In contrast, the compressive dielectric is configured to experience compressive stress at an upper surface and tensile stress at a lower surface (e.g., the compressive dielectric will warp concave up). As a result, stress in the semiconductor device assembly can be reduced and overall yield can be improved.

First claim

What is claimed is:

1 . A semiconductor device assembly, comprising:
a first semiconductor die having a first side at which a first dielectric material and first contact pads are disposed; and a second semiconductor die having:
a second side at which a second dielectric material and second contact pads are disposed; and
a third side opposite the second side,
wherein the second semiconductor die is coupled with the first semiconductor die such that the first contact pads and the second contact pads form interconnects electrically coupling the first semiconductor die and the second semiconductor die and the first dielectric material and the second dielectric material are directly bonded;
a third dielectric material disposed at the first side of the first semiconductor die and beyond a footprint of the second semiconductor die; and a fourth dielectric material disposed at least partially over the third dielectric material and outside of the footprint of the second semiconductor die, wherein the third dielectric material comprises one of:
a tensile dielectric material configured to experience tensile stress at a first upper surface and compressive stress at a first lower surface; and
a compressive dielectric material configured to experience compressive stress at a second upper surface and tensile stress at a second lower surface, and
wherein the fourth dielectric material comprises the other of:
the tensile dielectric material; and
the compressive dielectric material.

2 . The semiconductor device assembly of claim 1 , wherein the third dielectric material extends at least partially up an edge of the second semiconductor die between the second side and the third side.

3 . The semiconductor device assembly of claim 1 , wherein the third dielectric material comprises silicon oxide.

4 . The semiconductor device assembly of claim 1 , wherein the fourth dielectric material comprises silicon nitride.

5 . The semiconductor device assembly of claim 1 , wherein:
a fifth dielectric material disposed at the third side; and the third dielectric material contacts the fifth dielectric material.

6 . The semiconductor device assembly of claim 1 , wherein:
the second semiconductor die further comprises:
through-silicon vias (TSVs) extending from the second side to the third side;
third contact pads disposed at the third side on the TSVs; and
a fifth dielectric material disposed at the third side; and
the semiconductor device assembly further comprises:
a third semiconductor die having:
a fourth side at which a sixth dielectric material and fourth contact pads are disposed; and
a fifth side opposite the fourth side,
wherein the third semiconductor die is coupled with the second semiconductor die such that the third contact pads and the fourth contact pads form second interconnects electrically coupling the second semiconductor die and the third semiconductor die and the fifth dielectric material and the sixth dielectric material are directly bonded;

a seventh dielectric material disposed above the fourth dielectric material,
wherein the seventh dielectric material comprises one of:
an additional tensile dielectric material; and
an additional compressive dielectric material; and

an eighth dielectric material disposed above the fourth dielectric material,
wherein the eighth dielectric material comprises the other of:
the additional tensile dielectric material; and
the additional compressive dielectric material.

7 . The semiconductor device assembly of claim 6 , wherein the fifth dielectric material is disposed at least partially over the fourth dielectric material such that the fifth dielectric material is disposed at least partially between the fourth dielectric material and the seventh dielectric material.

8 . The semiconductor device assembly of claim 1 , wherein a thickness of the third dielectric material is different from a thickness of the fourth dielectric material.

9 . A method for fabricating a semiconductor device assembly, comprising:
providing a first semiconductor die having a first side at which a first dielectric material and first contact pads are disposed; providing a second semiconductor die having a second side at which a second dielectric material and second contact pads are disposed; coupling the second semiconductor die to the first semiconductor die such that the first contact pads and the second contact pads form interconnects and the first dielectric material and the second dielectric material directly bond; disposing a third dielectric material at the first side of the first semiconductor die and beyond a footprint of the second semiconductor die; and disposing a fourth dielectric material at least partially over the third dielectric material and outside of the footprint of the second semiconductor die, wherein the third dielectric material comprises one of:
a tensile dielectric material configured to experience tensile stress at a first upper surface and compressive stress at a first lower surface; and
a compressive dielectric material configured to experience compressive stress at a second upper surface and tensile stress at a second lower surface, and
wherein the fourth dielectric material comprises the other of:
the tensile dielectric material; and
the compressive dielectric material.

10 . The method of claim 9 , further comprising:
disposing the third dielectric material and the fourth dielectric material at least partially over a third side of the second semiconductor die; and thinning the third dielectric material and the fourth dielectric material to expose the third side of the second semiconductor die.

11 . The method of claim 9 , further comprising disposing the third dielectric material along an edge of the second semiconductor die.

12 . The method of claim 9 , wherein the first semiconductor die is included in a wafer of semiconductor dies that further includes a third semiconductor die, the method further comprising:
coupling a fourth semiconductor die to the third semiconductor die; and disposing the third dielectric material and the fourth dielectric material at a first side of the wafer of semiconductor dies between the second semiconductor die and the fourth semiconductor die.

13 . The method of claim 12 , further comprising:
disposing a fifth dielectric material at least partially over the second semiconductor die, the fourth semiconductor die, and the fourth dielectric material; and coupling a fifth semiconductor die to the second semiconductor die through the fifth dielectric material.

14 . The method of claim 9 , further comprising, after disposing the third dielectric material and the fourth dielectric material, disposing through-silicon vias in the second semiconductor die.

15 . The method of claim 9 , further comprising:
determining that the first side of the first semiconductor die is configured to experience tensile stress; and selecting the tensile dielectric material as the third dielectric material based on the first side of the first semiconductor die being configured to experience tensile stress.

16 . The method of claim 9 , further comprising:
determining that the first side of the first semiconductor die is configured to experience compressive stress; and selecting the compressive dielectric material as the third dielectric material based on the first side of the first semiconductor die being configured to experience compressive stress.

17 . The method of claim 9 , further comprising:
determining that the first

Assignees

• Micron Technology Inc

Inventors

• Zhou Wei
• Street Bret K
• Singh Akshay N
• Parekh Kunal R
• Bhushan Bharat

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W72/0198

  batch processes · CPC title