Semiconductor memory devices, methods for fabricating the same and electronic systems including the same

Patent metadata

Field	Value
Publication number	US-2025071992-A1
Application number	US-202418604586-A
Country	US
Kind code	A1
Filing date	Mar 14, 2024
Priority date	Aug 25, 2023
Publication date	Feb 27, 2025
Grant date	—

Abstract

A semiconductor memory device may include a cell substrate including a first surface and a second surface opposite to the first surface, and a landing pattern including a third surface and a fourth surface opposite to the third surface, with the landing pattern spaced apart from the cell substrate in a horizontal direction. The semiconductor memory device may include a plurality of gate electrodes sequentially stacked on the first surface and the third surface, a channel structure on the cell substrate, the channel structure extending vertically and intersecting the plurality of gate electrodes, an upper insulating film covering the second surface and the fourth surface, an input/output pad on the upper insulating film, the input/output pad overlapping at least a portion of the plurality of gate electrodes in the vertical direction, and a support contact extending through the upper insulating film and connecting the landing pattern and the input/output pad.

First claim

1 . A semiconductor memory device comprising:
a cell substrate including a first surface and a second surface opposite to the first surface; a landing pattern including a third surface and a fourth surface opposite to the third surface, the landing pattern spaced apart from the cell substrate in a horizontal direction; a plurality of gate electrodes sequentially stacked on the first surface and the third surface; a channel structure on the cell substrate, the channel structure extending in a vertical direction that intersects the first surface, the channel structure intersecting the plurality of gate electrodes; an upper insulating film that covers the second surface and the fourth surface; an input/output pad on the upper insulating film, the input/output pad overlapping at least a portion of the plurality of gate electrodes in the vertical direction; and a support contact that extends through the upper insulating film and connects the landing pattern and the input/output pad.

2 . The semiconductor memory device of claim 1 , further comprising a contact plug spaced apart from the landing pattern in the horizontal direction, extending in the vertical direction and connected to the input/output pad.

3 . The semiconductor memory device of claim 2 , further comprising:
a peripheral circuit substrate including a fifth surface that faces the first surface and the third surface; and a peripheral circuit element on the fifth surface, wherein the contact plug electrically connects the input/output pad and the peripheral circuit element.

4 . The semiconductor memory device of claim 1 , wherein the cell substrate and the landing pattern include the same material.

5 . The semiconductor memory device of claim 4 , wherein the cell substrate and the landing pattern each include polysilicon doped with impurities.

6 . The semiconductor memory device of claim 1 , wherein the first surface and the third surface are coplanar, and
wherein the second surface and the fourth surface are coplanar.

7 . The semiconductor memory device of claim 1 , wherein a width of the support contact decreases in a direction toward the landing pattern.

8 . The semiconductor memory device of claim 1 , wherein a lower surface of the support contact is between the third surface and the fourth surface.

9 . The semiconductor memory device of claim 1 , wherein a thickness of the upper insulating film is in a range from 300 nm to 1000 nm, inclusive.

10 . The semiconductor memory device of claim 1 , further comprising an insulating substrate between the cell substrate and the landing pattern, the insulating substrate electrically separating the cell substrate and the landing pattern.

11 - 12 . (canceled)

13 . A semiconductor memory device comprising:
a peripheral circuit structure including a peripheral circuit substrate and a peripheral circuit element on the peripheral circuit substrate; and a cell structure stacked on the peripheral circuit structure, wherein the cell structure includes: a cell substrate including a first surface that faces the peripheral circuit structure and a second surface opposite to the first surface; a landing pattern including a third surface that faces the peripheral circuit structure and a fourth surface opposite to the third surface, the landing pattern spaced apart from the cell substrate in a horizontal direction; a stacked structure including a plurality of mold insulating films and a plurality of gate electrodes alternately stacked on the first surface and the third surface; a channel structure that extends in a vertical direction that intersects the first surface, the channel structure extending through the stacked structure; an input/output pad on the second surface and the fourth surface, the input/output pad overlapping at least a portion of the stacked structure in the vertical direction, a contact plug that extends in the vertical direction and electrically connects the peripheral circuit element and the input/output pad, an upper insulating film interposed between the cell substrate and the input/output pad and between the landing pattern and the input/output pad, and a support contact that extends through the upper insulating film and connects the landing pattern and the input/output pad.

14 . The semiconductor memory device of claim 13 , wherein the contact plug includes a first plug pattern that extends in the vertical direction on a first side of the stacked structure, and a second plug pattern that extends through the upper insulating film and connects the input/output pad and the first plug pattern, and
wherein, with the third surface as a reference, a depth to which the support contact extends is smaller than a depth to which the second plug pattern extends.

15 . The semiconductor memory device of claim 14 , wherein a width of the first plug pattern decreases in a direction toward the second plug pattern, and
a width of the second plug pattern decreases in a direction toward the first plug pattern.

16 . (canceled)

17 . The semiconductor memory device of claim 13 , wherein the input/output pad is completely overlapped by the stacked structure in the vertical direction.

18 . The semiconductor memory device of claim 17 , wherein the contact plug extends in the vertical direction and extends through the stacked structure.

19 . The semiconductor memory device of claim 17 , wherein the cell substrate surrounds at least a portion of a perimeter of the landing pattern when viewed in a plan view.

20 . The semiconductor memory device of claim 13 , wherein the cell structure further includes:
a word line cut area that extends in a first direction and intersects the vertical direction through the stacked structure; and a bit line that extends between the peripheral circuit structure and the stacked structure in a second direction that intersects the vertical direction and the first direction, wherein the channel structure connects the cell substrate and the bit line.

21 . The semiconductor memory device of claim 20 , wherein the cell structure further includes a cell wiring structure electrically connected to the plurality of gate electrodes, the bit line, and the contact plug,
wherein the peripheral circuit structure further includes a peripheral circuit wiring structure electrically connected to the peripheral circuit element, and wherein the cell wiring structure and the peripheral circuit wiring structure are bonded to each other.

22 - 24 . (canceled)

25 . An electronic system comprising:
a main board; a semiconductor memory device including a peripheral circuit structure and a cell structure sequentially stacked on the main board; and a controller on the main board, the controller electrically connected to the semiconductor memory device, wherein the cell structure includes: a cell substrate including a first surface and a second surface opposite to the first surface; a landing pattern including a third surface and a fourth surface opposite to the third surface, the landing pattern spaced apart from the cell substrate in a horizontal direction; a plurality of gate electrodes sequentially stacked on the first surface and the third surface; a channel structure on the cell substrate, the channel structure extending in a vertical direction that intersects the first surface, the channel structure intersecting the plurality of gate electrodes, an upper insulating film that covers the second surface and the four

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Min Yong
• Lee Se Hoon
• Kim Jun Hyoung
• Kim Ji Young
• Sung Suk Kang

Classifications

• H10W90/752

  between stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10B80/00

  Assemblies of multiple devices comprising at least one memory device covered by this subclass · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title