Semiconductor device

Patent metadata

Field	Value
Publication number	US-2025070022-A1
Application number	US-202418634325-A
Country	US
Kind code	A1
Filing date	Apr 12, 2024
Priority date	Aug 21, 2023
Publication date	Feb 27, 2025
Grant date	—

Abstract

A semiconductor device may include a substrate including a cell array region, a core region, and a peripheral circuit region, a core circuit wiring on the core region of the substrate, a core signal wiring overlapping the core circuit wiring, and a contact plug between the core circuit wiring and the core signal wiring. The contact plug may connect the core circuit wiring to the core signal wiring. A positional relationship between the core signal wiring and the contact plug may be different depending on distance from the peripheral circuit region.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate including a cell array region, a core region, and a peripheral circuit region; a core circuit wiring on the core region of the substrate; a core signal wiring overlapping the core circuit wiring; and a contact plug between the core circuit wiring and the core signal wiring and connecting the core circuit wiring to the core signal wiring, wherein a positional relationship between the core signal wiring and the contact plug is different depending on a distance of the contact plug from the peripheral circuit region.

2 . The semiconductor device of claim 1 , wherein
the core signal wiring comprises a first edge and a second edge opposite the first edge; the first edge is closer to the peripheral circuit region than the second edge; a first distance from the first edge of the core signal wiring to the contact plug gradually increases as the distance of contact plug from the peripheral circuit region increases.

3 . The semiconductor device of claim 2 , wherein a second distance from the second edge of the core signal wiring to the contact plug gradually decreases as the distance of the contact plug from the peripheral circuit region increases.

4 . The semiconductor device of claim 3 , wherein
the first distance is smaller than the second distance at a closest point to the peripheral circuit region; the first distance is greater than the second distance at a farthest point from the peripheral circuit region; and the first distance and the second distance are equal at a center point between the closest point to the peripheral circuit region and the farthest point from the peripheral circuit region.

5 . The semiconductor device of claim 1 , wherein
the substrate includes a plurality of cell array regions arranged along a first direction and a second direction at both sides of the peripheral circuit region, the core region is between the plurality of cell array regions, and the positional relationship between the core signal wiring and the contact plug in the core region positioned on a left side of the peripheral circuit region is symmetrical to the positional relationship between the core signal wiring and the contact plug in the core region positioned on a right side of the peripheral circuit region.

6 . The semiconductor device of claim 5 , wherein
the peripheral circuit region extends along the second direction, the plurality of cell array regions and the core region are positioned on the both sides of the peripheral circuit region along the first direction.

7 . The semiconductor device of claim 6 , wherein
in an area of the core region positioned on the right side of the peripheral circuit region, a distance from a left-side edge of the core signal wiring to the contact plug gradually increases as the distance of the contact plug from the peripheral circuit region increases, and a distance from a right-side edge of the core signal wiring to the contact plug gradually decreases as the distance of the contact plug from the peripheral circuit region increases.

8 . The semiconductor device of claim 7 , wherein
at a closest point to the peripheral circuit region in the area of the core region positioned on the right side of the peripheral circuit region, the distance from the left-side edge of the core signal wiring to the contact plug is smaller than the distance from the right-side edge of the core signal wiring to the contact plug, and at a farthest point from the peripheral circuit region in the area of the core region positioned on the right side of the peripheral circuit region, the distance from the left-side edge of the core signal wiring to the contact plug is greater than the distance from the right-side edge of the core signal wiring to the contact plug.

9 . The semiconductor device of claim 6 , wherein
in an area of the core region positioned on the left side of the peripheral circuit region, a distance from a right-side edge of the core signal wiring to the contact plug gradually increases as the distance of the contact plug from the peripheral circuit region increases, and a distance from a left-side edge of the core signal wiring to the contact plug gradually decreases as the distance of the contact plug from the peripheral circuit region increases.

10 . The semiconductor device of claim 9 , wherein
at a closest point to the peripheral circuit region among the area of the core region positioned on the left side of the peripheral circuit region, the distance from the left-side edge of the core signal wiring to the contact plug is greater than the distance from the right-side edge of the core signal wiring to the contact plug; and at a farthest point from the peripheral circuit region among the core regions positioned on the right side of the peripheral circuit region, the distance from the left-side edge of the core signal wiring to the contact plug is smaller than the distance from the right-side edge of the core signal wiring to the contact plug.

11 . The semiconductor device of claim 1 , wherein a positional relationship between the core circuit wiring and the contact plug is constant regardless of the distance of the contact plug from the peripheral circuit region.

12 . The semiconductor device of claim 1 , further comprising:
a word line on the cell array region of the substrate; a bit line crossing the word line; a bit line contact pattern connecting between a first active region of the substrate and the bit line; a landing pad connected to the first active region of the substrate; and a lower contact between the landing pad and the first active region of the substrate an connecting the landing pad to the first active region, wherein the core circuit wiring is in a same layer as the landing pad.

13 . The semiconductor device of claim 12 , further comprising:
an insulating layer on the substrate; a capacitor connected to the landing pad; a cell signal wiring connected to the capacitor; and a capacitor contact via between the capacitor and the cell signal wiring and connecting the capacitor to the cell signal wiring, wherein a level of the core signal wiring above the substrate is in the same as a level of the cell signal wiring above the substrate, and the contact plug and the capacitor contact via each extend through the insulating layer.

14 . The semiconductor device of claim 1 , further comprising:
a gate stack on the core region of the substrate, wherein the substrate includes an impurity region positioned at both sides of the gate stack, and the core circuit wiring is connected to the impurity region.

15 . A semiconductor device, comprising:
a substrate including a peripheral circuit region, a plurality of cell array regions at both sides of the peripheral circuit region and arranged along a first direction and a second direction, and a core region between the plurality of cell array regions; a core circuit wiring on the core region of the substrate; a core signal wiring overlapping the core circuit wiring; and a contact plug between the core circuit wiring and the core signal wiring and connecting the core circuit wiring to the core signal wiring, wherein a first distance from a first edge of the core signal wiring to the contact plug gradually changes as a distance of the contact plug from the peripheral circuit region increases.

16 . The semiconductor device of claim 15 , wherein
the core signal wiring comprises a second edge opposite the first edge; the first edge is closer to the peripheral circuit

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Dongkyun
• Kim Hyejin
• Son Yonghyeok
• Sim Jichang
• Lee Joo-Sung
• Cho Yujin

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10B80/00

  Assemblies of multiple devices comprising at least one memory device covered by this subclass · CPC title

• H10B12/315

  with the capacitor higher than a bit line · CPC title

• H10B12/09

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title