Addition method, semiconductor device, and electronic device

Patent metadata

Field	Value
Publication number	US-2025068391-A1
Application number	US-202418945896-A
Country	US
Kind code	A1
Filing date	Nov 13, 2024
Priority date	Nov 17, 2017
Publication date	Feb 27, 2025
Grant date	—

Abstract

A multiplier circuit includes a first circuit comprising a first transistor, a second transistor, a first capacitor, and a second capacitor. It further includes a second circuit comprising a third transistor, a fourth transistor, a third capacitor, and a fourth capacitor.

First claim

1 . A multiplier circuit comprising:
a first circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, and a first capacitor, wherein a gate of the first transistor is electrically connected to one of a source and a drain of the first transistor through the first switch, wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the third transistor through the eighth switch, wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the fifth transistor through the ninth switch, wherein a gate of the second transistor is electrically connected to one of a source and a drain of the second transistor through the second switch, wherein the gate of the second transistor is electrically connected to one electrode of the first capacitor, wherein the other of the source and the drain of the second transistor is electrically connected to the other electrode of the first capacitor, wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the fourth transistor through the third switch and the sixth switch, wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the sixth transistor through the fifth switch, wherein the other of the source and the drain of the second transistor is electrically connected to one electrode of the fourth switch through the fifth switch, wherein the one of the source and the drain of the third transistor is electrically connected to the one of the source and the drain of the fourth transistor through the seventh switch, and wherein a gate of the fifth transistor is electrically connected to a gate of the sixth transistor and the other electrode of the fourth switch.

2 . The multiplier circuit according to claim 1 ,
wherein the other of the source and the drain of the first transistor is electrically connected to a converter circuit through a tenth switch.

3 . The multiplier circuit according to claim 1 , further comprising a multiplication cell,
wherein the multiplication cell comprises a seventh transistor and a second capacitor, wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the seventh transistor, and wherein a gate of the seventh transistor is electrically connected to one electrode of the second capacitor.

4 . The multiplier circuit according to claim 1 , further comprising a reference cell,
wherein the reference cell comprises an eighth transistor and a third capacitor, wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the eighth transistor, and wherein a gate of the eighth transistor is electrically connected to one electrode of the third capacitor.

5 . The multiplier circuit according to claim 1 , wherein all of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are n-channel transistors.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Kimura Hajime
• Fukutome Takahiro

Classifications

• G06G7/16

  for multiplication or division {(G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00)} · CPC title

• G06F7/4991 Primary

  Overflow or underflow · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F7/57

  Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)} · CPC title

• G06F7/501

  Half or full adders, i.e. basic adder cells for one denomination · CPC title