Power semiconductor package

Patent metadata

Field	Value
Publication number	US-2025062290-A1
Application number	US-202418934846-A
Country	US
Kind code	A1
Filing date	Nov 1, 2024
Priority date	May 4, 2022
Publication date	Feb 20, 2025
Grant date	—

Abstract

A power semiconductor package includes a plurality of first power semiconductor dies attached to a first metallization layer and a plurality of second power semiconductor dies attached to a second metallization layer. A first structured metal frame disposed above the first metallization layer is electrically connected to a load terminal of each first power semiconductor die. A second structured metal frame disposed above the second metallization layer is electrically connected to a load terminal of each second power semiconductor die and to the first metallization layer. A first lead is electrically connected to the second metallization layer. A second lead is electrically connected to the second metallization layer. A third lead interposed between the first and second leads is electrically connected to the first structured metal frame. A fourth lead is electrically connected to the second structured metal frame.

First claim

What is claimed is:

1 . A power semiconductor package, comprising:
a plurality of first power semiconductor dies attached to a first metallization layer; a plurality of second power semiconductor dies attached to a second metallization layer; a first structured metal frame disposed above the first metallization layer and electrically connected to a load terminal of each power semiconductor die of the plurality of first power semiconductor dies; a second structured metal frame disposed above the second metallization layer and electrically connected to a load terminal of each power semiconductor die of the plurality of second power semiconductor dies and to the first metallization layer; and a lead frame disposed above the first and the second structured metal frames and comprising:
a first lead electrically connected to the second metallization layer;
a second lead electrically connected to the second metallization layer;
a third lead interposed between the first and second leads and electrically connected to the first structured metal frame; and
a fourth lead electrically connected to the second structured metal frame.

2 . The power semiconductor package of claim 1 , further comprising a mold compound encasing the plurality of first power semiconductor dies and the plurality of second power semiconductor dies, and at least partly encasing the first lead, the second lead, the third lead and the fourth lead.

3 . The power semiconductor package of claim 2 , wherein the first lead protrudes from a first side face of the mold compound, and wherein the second lead protrudes from the first side face of the mold compound.

4 . The power semiconductor package of claim 3 , wherein the third lead protrudes from the first side face of the mold compound between the first lead and the second lead.

5 . The power semiconductor package of claim 3 , wherein the fourth lead protrudes from a second side face of the mold compound opposite the first side face.

6 . The power semiconductor package of claim 3 , further comprising:
a first press-fit pin attached to the first structured metal frame and protruding through a front surface of the mold compound, the mold compound also having a back surface opposite the front surface, the first and second side faces of the mold compound extending between the front and back surfaces; and a second press-fit pin attached to the second structured metal frame and protruding through the front surface of the mold compound.

7 . The power semiconductor package of claim 3 , further comprising:
a first gate metallization embedded in the mold compound above the first metallization layer and electrically connected to a gate terminal of each power semiconductor die included in the plurality of first power semiconductor dies; a second gate metallization embedded in the mold compound above the second metallization layer and electrically connected to a gate terminal of each power semiconductor die included in the plurality of second power semiconductor dies; a first press-fit pin attached to the first gate metallization and protruding through a front surface of the mold compound, the mold compound also having a back surface opposite the front surface, the first and second side faces of the mold compound extending between the front and back surfaces; and a second press-fit pin attached to the second gate metallization and protruding through the front surface of the mold compound.

8 . The power semiconductor package of claim 1 , wherein the plurality of second power semiconductor dies and the plurality of first power semiconductor dies are electrically connected to form a half bridge.

9 . The power semiconductor package of claim 8 , wherein the first lead forms a first DC+ lead for the half bridge, wherein the second lead forms a second DC+ lead for the half bridge, wherein the third lead forms a DC-lead for the half bridge, and wherein the fourth lead forms a switch node lead for the half bridge.

10 . The power semiconductor package of claim 1 , wherein the lead frame is thicker than both the first structured metal frame and the second structured metal frame.

11 . The power semiconductor package of claim 1 , wherein both the first structured metal frame and the second structured metal frame have a thickness less than 0.5 mm, and wherein the lead frame has a thickness greater than 0.5 mm and less than 1 mm.

12 . The power semiconductor package of claim 1 , wherein the first lead and the second lead are each thicker than both the first structured metal frame and the second structured metal frame.

13 . The power semiconductor package of claim 1 , wherein the third lead is laterally interposed between the first lead and the second lead, and wherein the third lead is vertically connected to the first structured metal frame and thicker than both the first structured metal frame and the second structured metal frame.

14 . The power semiconductor package of claim 1 , wherein the fourth lead is vertically connected to the second structured metal frame and thicker than both the first structured metal frame and the second structured metal frame.

15 . The power semiconductor package of claim 1 , further comprising:
a sensor, wherein the lead frame comprises a metal structure electrically connected to the sensor.

Assignees

• Infineon Technologies Ag

Inventors

• Nikitin Ivan
• Scharf Thorsten
• Bãssler Marco
• Grassmann Andreas
• Jakobi Waldemar

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title